TY - GEN
T1 - A method of temperature drift compensation for pulse synchronization in high-speed signal acquisition
AU - Wang, Longhui
AU - Liu, Guoman
AU - Wang, Junling
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/26
Y1 - 2017/10/26
N2 - In order to ensure timing sequence and synchronization performance between different pulses not affected by temperature drift, a method of detecting temperature and compensating temperature drift based on FPGA was proposed, which can ensure data synchronization between different pulses at different temperatures. Because FPGA temperature influenced temperature drift, this method was used to detect temperature by using the temperature sensor of Virtex-6 FPGA family, and to compensate temperature drift by delaying reference clock according to temperature delay parameters at different temperatures, so that the timing sequence was not influenced by temperature drift. The temperature delay parameters were measured in the case of stable operation of the system for a long time and stored in ROM. When temperature changed, FPGA read the corresponding temperature delay parameter from the ROM. Through the point-frequency signal test, synchronization deviations between different pulses at different temperatures (-20°C∼60°C) are not more than 5ps. This method solves the problem of temperature drift effectively and has practical value.
AB - In order to ensure timing sequence and synchronization performance between different pulses not affected by temperature drift, a method of detecting temperature and compensating temperature drift based on FPGA was proposed, which can ensure data synchronization between different pulses at different temperatures. Because FPGA temperature influenced temperature drift, this method was used to detect temperature by using the temperature sensor of Virtex-6 FPGA family, and to compensate temperature drift by delaying reference clock according to temperature delay parameters at different temperatures, so that the timing sequence was not influenced by temperature drift. The temperature delay parameters were measured in the case of stable operation of the system for a long time and stored in ROM. When temperature changed, FPGA read the corresponding temperature delay parameter from the ROM. Through the point-frequency signal test, synchronization deviations between different pulses at different temperatures (-20°C∼60°C) are not more than 5ps. This method solves the problem of temperature drift effectively and has practical value.
KW - Virtex-6 FPGA
KW - pulse synchronization
KW - system monitor IP core
KW - temperature drift delay compensation module
UR - http://www.scopus.com/inward/record.url?scp=85040131352&partnerID=8YFLogxK
U2 - 10.1109/CCSSE.2017.8087988
DO - 10.1109/CCSSE.2017.8087988
M3 - Conference contribution
AN - SCOPUS:85040131352
T3 - 2017 3rd IEEE International Conference on Control Science and Systems Engineering, ICCSSE 2017
SP - 529
EP - 534
BT - 2017 3rd IEEE International Conference on Control Science and Systems Engineering, ICCSSE 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd IEEE International Conference on Control Science and Systems Engineering, ICCSSE 2017
Y2 - 17 August 2017 through 19 August 2017
ER -