TY - GEN
T1 - A Low Latency Hardware Implementation Architecture for Polar Code
AU - Liu, Minnan
AU - Chen, Chaofan
AU - Ma, Yongfeng
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - Polar codes are the only constructive codes that are able to reach the Shannon limit. Due to excellent decoding performance and low implementation complexity, polar codes have been adopted in the control channel coding standard of 5G mobile communication. With the development of mobile communication technology, performance indicators such as end-to-end delay, user experience rate and mobility have become the focus of 5G technology, which requires more efficient coding and decoding rates for channel coding. However, the existing SCL decoding algorithm of the polar code, due to the expansion of the search path, causes a large amount of delay in decoding, which limits the improvement of the decoding rate. In this paper, a low latency polar code decoder is proposed for the above scenario. When code length is 1024 bits, and search path width is four, the proposed decoder can achieve the effect of improving the throughput by 46% only at the expense of 2% resources compared with the traditional decoders.
AB - Polar codes are the only constructive codes that are able to reach the Shannon limit. Due to excellent decoding performance and low implementation complexity, polar codes have been adopted in the control channel coding standard of 5G mobile communication. With the development of mobile communication technology, performance indicators such as end-to-end delay, user experience rate and mobility have become the focus of 5G technology, which requires more efficient coding and decoding rates for channel coding. However, the existing SCL decoding algorithm of the polar code, due to the expansion of the search path, causes a large amount of delay in decoding, which limits the improvement of the decoding rate. In this paper, a low latency polar code decoder is proposed for the above scenario. When code length is 1024 bits, and search path width is four, the proposed decoder can achieve the effect of improving the throughput by 46% only at the expense of 2% resources compared with the traditional decoders.
KW - decoding algorithm
KW - hardware architecture
KW - latency
KW - polar codes
UR - http://www.scopus.com/inward/record.url?scp=85078102202&partnerID=8YFLogxK
U2 - 10.1109/ICCT46805.2019.8947244
DO - 10.1109/ICCT46805.2019.8947244
M3 - Conference contribution
AN - SCOPUS:85078102202
T3 - International Conference on Communication Technology Proceedings, ICCT
SP - 1443
EP - 1448
BT - 2019 IEEE 19th International Conference on Communication Technology, ICCT 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 19th IEEE International Conference on Communication Technology, ICCT 2019
Y2 - 16 October 2019 through 19 October 2019
ER -