TY - GEN
T1 - A low data rate FM-UWB transmitter with Δ-Σ based sub-carrier modulation and quasi-continuous frequency-locked loop
AU - Zhou, Bo
AU - He, Rui
AU - Qiao, Jian
AU - Liu, Jinghui
AU - Rhee, Woogeun
AU - Wang, Zhihua
PY - 2010
Y1 - 2010
N2 - This paper describes the architecture and circuit design of a low data rate FM-UWB transmitter. A Δ-Σ fractional-N PLL with a multi-phase relaxation oscillator is designed to enable sub-carrier modulation with reduced quantization noise. The triangular waveform output of the relaxation oscillator directly modulates an LC VCO to have the UWB-compliant spectrum. The center frequency of the LC VCO is quasi-continuously tuned by a Δ-Σ DAC based frequency-locked loop with the power consumption of 1.1mW. The 3.43-4.03GHz FM-UWB transmitter implemented in 0.18μm CMOS consumes the total power of 9.6mW.
AB - This paper describes the architecture and circuit design of a low data rate FM-UWB transmitter. A Δ-Σ fractional-N PLL with a multi-phase relaxation oscillator is designed to enable sub-carrier modulation with reduced quantization noise. The triangular waveform output of the relaxation oscillator directly modulates an LC VCO to have the UWB-compliant spectrum. The center frequency of the LC VCO is quasi-continuously tuned by a Δ-Σ DAC based frequency-locked loop with the power consumption of 1.1mW. The 3.43-4.03GHz FM-UWB transmitter implemented in 0.18μm CMOS consumes the total power of 9.6mW.
UR - http://www.scopus.com/inward/record.url?scp=79952836465&partnerID=8YFLogxK
U2 - 10.1109/ASSCC.2010.5716550
DO - 10.1109/ASSCC.2010.5716550
M3 - Conference contribution
AN - SCOPUS:79952836465
SN - 9781424482979
T3 - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
SP - 33
EP - 36
BT - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
T2 - 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Y2 - 8 November 2010 through 10 November 2010
ER -