A four-bank memory design of optimized semi-parallel polar decoder

Shiwen Xing, Yun Nan Chang, Liang Chen*

*此作品的通讯作者

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

Polar code, which is capable of achieving channel capacity, is known as a promising forward error correction (FEC) code in coding theory. In this paper, a four-bank memory architecture is proposed for polar decoder to store the initial and the intermediate processing data. Based on the proposed load-balance data allocation scheme, each memory bank is able to be equipped with only two access ports, while providing enough data bandwidth demand. Besides, the proposed semi-parallel successive cancellation (SC) polar decoder is optimized by employing the efficient p node and the merged computation of f and g nodes to reduce the decoding latency, which can at most get 62.5% speed improvement with enough processing elements (PEs). In addition, the proposed four-bank memory design can reduce the overall size of memory especially with higher level of parallelism.

源语言英语
主期刊名2017 9th IEEE International Conference on Communication Software and Networks, ICCSN 2017
出版商Institute of Electrical and Electronics Engineers Inc.
80-84
页数5
ISBN(电子版)9781509038220
DOI
出版状态已出版 - 19 12月 2017
活动9th IEEE International Conference on Communication Software and Networks, ICCSN 2017 - Guangzhou, 中国
期限: 6 5月 20178 5月 2017

出版系列

姓名2017 9th IEEE International Conference on Communication Software and Networks, ICCSN 2017
2017-January

会议

会议9th IEEE International Conference on Communication Software and Networks, ICCSN 2017
国家/地区中国
Guangzhou
时期6/05/178/05/17

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引用此

Xing, S., Chang, Y. N., & Chen, L. (2017). A four-bank memory design of optimized semi-parallel polar decoder. 在 2017 9th IEEE International Conference on Communication Software and Networks, ICCSN 2017 (页码 80-84). (2017 9th IEEE International Conference on Communication Software and Networks, ICCSN 2017; 卷 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCSN.2017.8230083