@inproceedings{0771732c6b1a4569984b3133a3a330ed,
title = "A fast-settling fractional-N PLL with presetting frequency and dynamic bandwidth control",
abstract = "A fast-settling dual-path fractional-N phase-locked loop(PLL) is presented in this paper, which is applied for frequent current charging and discharging. Compared with the conventional phase-locked loop, this one is significantly able to reduce the settling time with hybrid approaches. By employing direct presetting frequency, based on frequency-locked loop(FLL), the process locking is accelerated. To achieve low phase noise, 20-bits delta-sigma modulator is employed in PLL. Dynamic bandwidth is beneficial for both of them and results a smooth transition. Besides, the dual-path fractional-N PLL compensates the nonlinearity from the charge pump (CP), and provides a wider tuning range. Using the 0.6V supply voltage for 65nm CMOS, a 900MHz fractional-N PLL with mixed techniques exhibits less than 2.5μs transient settling time according the simulation results.",
keywords = "Dynamic bandwidth, Fractional-N phase-locked loop (PLL), Presetting frequency, Settling time",
author = "Yao Li and Bo Zhou and Fuyuan Zhao",
note = "Publisher Copyright: {\textcopyright} 2019 The authors and IOS Press. All rights reserved.; 5th International Conference on Fuzzy Systems and Data Mining, FSDM 2019 ; Conference date: 18-10-2019 Through 21-10-2019",
year = "2019",
month = oct,
day = "2",
doi = "10.3233/FAIA190277",
language = "English",
series = "Frontiers in Artificial Intelligence and Applications",
publisher = "IOS Press BV",
pages = "1004--1011",
editor = "Tallon-Ballesteros, {Antonio J.}",
booktitle = "Fuzzy Systems and Data Mining V - Proceedings of FSDM 2019",
address = "Netherlands",
}