摘要
A 1.5-2.5 GHz current-mode logic (CML) ring oscillator-based supply-insensitive phase-locked loop (PLL) employing two different topologies of CML ring oscillators that compensate for the supply variations is presented. In addition, an on-chip calibration scheme is designed to ensure the voltage-controlled oscillators (VCOs) to operate at the optimum operating point where the PLL achieves nearly the best power supply rejection. This work shows more than 96% reduction in supply sensitivity of VCOs compared with the conventional topology. In addition, the sinusoidal jitter is improved by at least 70% closed-loop with the on-chip calibrations. The chip was fabricated in SMIC 0.18 μm CMOS process.
| 源语言 | 英语 |
|---|---|
| 文章编号 | 6987379 |
| 页（从-至） | 233-243 |
| 页数 | 11 |
| 期刊 | IEEE Transactions on Microwave Theory and Techniques |
| 卷 | 63 |
| 期 | 1 |
| DOI | |
| 出版状态 | 已出版 - 1 1月 2015 |
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Gui, X., Gao, P., & Chen, Z. (2015). A CML ring oscillator-based supply-insensitive PLL with on-chip calibrations. IEEE Transactions on Microwave Theory and Techniques, 63(1), 233-243. 文章 6987379. https://doi.org/10.1109/TMTT.2014.2376552