TY - GEN
T1 - A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS
AU - Wang, Zheng
AU - Chiang, Pei Yuan
AU - Nazari, Peyman
AU - Wang, Chun Cheng
AU - Chen, Zhiming
AU - Heydari, Payam
PY - 2013
Y1 - 2013
N2 - The vastly under-utilized spectrum in the sub-THz frequency range enables disruptive applications including 10Gb/s chip-to-chip wireless communications and imaging/spectroscopy. Owing to aggressive scaling in feature size and device fT/fmax, nanoscale CMOS technology potentially enables integration of sophisticated systems at this frequency range. For example, CMOS sub-THz signal sources and TRXs have been reported [1-4], employing techniques such as distributed active radiator (DAR) and super-harmonic signal generator. The lack of RF amplification in CMOS sub-THz TRXs reported in prior work, however, results in low efficiency (and thus higher power dissipation), and high noise-figure (NF). This paper addresses these issues by demonstrating a 210GHz TRX with on-off-keying (OOK) modulation incorporating a 2×2 TX antenna array, a 2×2 spatial combining power amplifier (PA), a fundamental frequency VCO, and a low noise amplifier (LNA) in a 32nm SOI CMOS process (fT/fmax=250/350GHz).
AB - The vastly under-utilized spectrum in the sub-THz frequency range enables disruptive applications including 10Gb/s chip-to-chip wireless communications and imaging/spectroscopy. Owing to aggressive scaling in feature size and device fT/fmax, nanoscale CMOS technology potentially enables integration of sophisticated systems at this frequency range. For example, CMOS sub-THz signal sources and TRXs have been reported [1-4], employing techniques such as distributed active radiator (DAR) and super-harmonic signal generator. The lack of RF amplification in CMOS sub-THz TRXs reported in prior work, however, results in low efficiency (and thus higher power dissipation), and high noise-figure (NF). This paper addresses these issues by demonstrating a 210GHz TRX with on-off-keying (OOK) modulation incorporating a 2×2 TX antenna array, a 2×2 spatial combining power amplifier (PA), a fundamental frequency VCO, and a low noise amplifier (LNA) in a 32nm SOI CMOS process (fT/fmax=250/350GHz).
UR - http://www.scopus.com/inward/record.url?scp=84876591875&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2013.6487670
DO - 10.1109/ISSCC.2013.6487670
M3 - Conference contribution
AN - SCOPUS:84876591875
SN - 9781467345132
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 136
EP - 137
BT - 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
T2 - 2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
Y2 - 17 February 2013 through 21 February 2013
ER -