3.5-Gb/s 0.35-μm CMOS data decision IC

Zheng Gu, Zhi Gong Wang, Huan Wang, Rui Tao, Tingting Xie, Shizhong Xie, Yi Dong

科研成果: 期刊稿件文章同行评审

摘要

A data decision IC is designed for STM-16 SDH-systems. A differential high-speed master-slave DFF is used for the decision function. Wide-band high-gain amplifiers are used for input and output data buffers to obtain high sensitivity and sufficient drive capability. The chip was realized in a 0.35-μm CMOS foundry technology. The chip size is 0.7 × 0.8 mm2. The supply voltage is 5 V and the current is 50 mA. A working data rate of higher than 3.5 Gb/s has been measured. The sensitivity is as low as 10-20 mV.

源语言英语
页(从-至)283-286
页数4
期刊Proceedings of SPIE - The International Society for Optical Engineering
4603
DOI
出版状态已出版 - 2001
已对外发布

指纹

探究 '3.5-Gb/s 0.35-μm CMOS data decision IC' 的科研主题。它们共同构成独一无二的指纹。

引用此

Gu, Z., Wang, Z. G., Wang, H., Tao, R., Xie, T., Xie, S., & Dong, Y. (2001). 3.5-Gb/s 0.35-μm CMOS data decision IC. Proceedings of SPIE - The International Society for Optical Engineering, 4603, 283-286. https://doi.org/10.1117/12.444577