TY - GEN
T1 - Using active cache to solve the bottleneck of bus in the parallel Radar signal process system
AU - Qin, Fei
AU - Wang, Zheng
AU - Long, Teng
PY - 2007
Y1 - 2007
N2 - Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result on an embedded signal processing system of four TigerSHARC101 DSPs.
AB - Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result on an embedded signal processing system of four TigerSHARC101 DSPs.
UR - http://www.scopus.com/inward/record.url?scp=34249282728&partnerID=8YFLogxK
U2 - 10.1109/ICOSP.2006.345996
DO - 10.1109/ICOSP.2006.345996
M3 - Conference contribution
AN - SCOPUS:34249282728
SN - 0780397371
SN - 9780780397378
T3 - International Conference on Signal Processing Proceedings, ICSP
BT - 8th International Conference on Signal Processing, ICSP 2006
T2 - 8th International Conference on Signal Processing, ICSP 2006
Y2 - 16 November 2006 through 20 November 2006
ER -