Using active cache to solve the bottleneck of bus in the parallel Radar signal process system

Fei Qin; Zheng Wang; Teng Long

doi:10.1109/ICOSP.2006.345996

Using active cache to solve the bottleneck of bus in the parallel Radar signal process system

Fei Qin^*, Zheng Wang, Teng Long

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result on an embedded signal processing system of four TigerSHARC101 DSPs.

Original language	English
Title of host publication	8th International Conference on Signal Processing, ICSP 2006
DOIs	https://doi.org/10.1109/ICOSP.2006.345996
Publication status	Published - 2007
Event	8th International Conference on Signal Processing, ICSP 2006 - Guilin, China Duration: 16 Nov 2006 → 20 Nov 2006

Publication series

Name	International Conference on Signal Processing Proceedings, ICSP
Volume	4

Conference

Conference	8th International Conference on Signal Processing, ICSP 2006
Country/Territory	China
City	Guilin
Period	16/11/06 → 20/11/06

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10.1109/ICOSP.2006.345996

Cite this

Qin, F., Wang, Z., & Long, T. (2007). Using active cache to solve the bottleneck of bus in the parallel Radar signal process system. In 8th International Conference on Signal Processing, ICSP 2006 Article 4129688 (International Conference on Signal Processing Proceedings, ICSP; Vol. 4). https://doi.org/10.1109/ICOSP.2006.345996

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title = "Using active cache to solve the bottleneck of bus in the parallel Radar signal process system",

abstract = "Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result on an embedded signal processing system of four TigerSHARC101 DSPs.",

author = "Fei Qin and Zheng Wang and Teng Long",

year = "2007",

doi = "10.1109/ICOSP.2006.345996",

language = "English",

isbn = "0780397371",

series = "International Conference on Signal Processing Proceedings, ICSP",

booktitle = "8th International Conference on Signal Processing, ICSP 2006",

note = "8th International Conference on Signal Processing, ICSP 2006 ; Conference date: 16-11-2006 Through 20-11-2006",

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Qin, F, Wang, Z & Long, T 2007, Using active cache to solve the bottleneck of bus in the parallel Radar signal process system. in 8th International Conference on Signal Processing, ICSP 2006., 4129688, International Conference on Signal Processing Proceedings, ICSP, vol. 4, 8th International Conference on Signal Processing, ICSP 2006, Guilin, China, 16/11/06. https://doi.org/10.1109/ICOSP.2006.345996

Using active cache to solve the bottleneck of bus in the parallel Radar signal process system. / Qin, Fei; Wang, Zheng; Long, Teng.
8th International Conference on Signal Processing, ICSP 2006. 2007. 4129688 (International Conference on Signal Processing Proceedings, ICSP; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Wang, Zheng

AU - Long, Teng

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AB - Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result on an embedded signal processing system of four TigerSHARC101 DSPs.

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M3 - Conference contribution

AN - SCOPUS:34249282728

SN - 0780397371

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Using active cache to solve the bottleneck of bus in the parallel Radar signal process system

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