Abstract
Matched-filter is widely used in real time signal processing, especially in Radar Signal Processing. This paper provides a novel structure of digital matched-filter used in tracking radar system. This design applies block-floating-point arithmetic to improve the precision. The whole digital matched-filter is implemented in only one chip of FPGA. This ASIC has two work modes: 512 points pulse compression and 256 points pulse, compression. It complements three channels of 512 points complex signal pulse compression in 102us.
| Original language | English |
|---|---|
| Title of host publication | Recent Advances in Circuits, Systems and Signal Processing |
| Publisher | World Scientific and Engineering Academy and Society |
| Pages | 98-103 |
| Number of pages | 6 |
| ISBN (Print) | 9608052645 |
| Publication status | Published - 2002 |
Keywords
- FFT
- FPGA
- Low power dissipation
- Matched-filter
- Parallel processing