Topology-Optimized Ultracompact All-Optical Logic Devices on Silicon Photonic Platforms

Lu He, Furong Zhang, Huizhen Zhang, Ling Jun Kong, Weixuan Zhang, Xingsheng Xu, Xiangdong Zhang*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

24 Citations (Scopus)

Abstract

The realization of all-optical integration and optical computing has always been our goal. One of the most significant challenges is to make integrated all-optical logic devices as small as possible. Here, we report the implementation of ultracompact all-optical logic devices and integrated chips on silicon photonic platforms by topology optimization. The footprint for the fabricated all-optical logic gates with XOR and OR functions is only 1.3 × 1.3 μm2 (∼0.84λ × 0.84λ) that are the smallest all-optical dielectric logic devices ever verified in experiments in the optical communication range. The ultralow loss of the optical signal is also demonstrated experimentally (-0.96 dB). Furthermore, an integrated chip containing seven major logic gates (AND, OR, NOT, NAND, NOR, XOR, and XNOR) and a half adder is fabricated, where the associated footprint is only 1.3 × 4.5 μm2. Our work opens up a new path toward practical all-optical integration and optical computing.

Original languageEnglish
Pages (from-to)597-604
Number of pages8
JournalACS Photonics
Volume9
Issue number2
DOIs
Publication statusPublished - 16 Feb 2022

Keywords

  • 1.3 × 1.3 μm
  • 50:50 beam splitter
  • half adder
  • logic gate
  • topology optimization

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