TY - GEN
T1 - Three-level Memory Access Architecture for FPGA-based Real-time Remote Sensing Image Processing System
AU - Zhang, Ning
AU - Wei, Xin
AU - Chen, Lei
AU - Chen, He
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - Recently, extensive convolutional neural network (CNN)-based methods have been used for real-time remote sensing image processing system. However, the huge storage requirement for model and input image bring a great challenge to hardware implement. In this paper, we propose a three-level memory access architecture for FPGA-based real-time remote sensing image processing system to meet the storage requirement. Moreover, in the proposed architecture, the computational throughput is well matched to the storage bandwidth, which improve the efficiency of arithmetic processing on the hardware platform. In the experiment, we applied the architecture to the hardware implementation of CNN, and implement on Xilinx ZYNQ xc7z035 platform. Our design is evaluated on a main part of the modified YOLOv2 framework [1]. The experimental results demonstrate that this design can access the off-chip memory efficiently, and can provide the required parameters and input data for the CNN on-chip pipeline processing.
AB - Recently, extensive convolutional neural network (CNN)-based methods have been used for real-time remote sensing image processing system. However, the huge storage requirement for model and input image bring a great challenge to hardware implement. In this paper, we propose a three-level memory access architecture for FPGA-based real-time remote sensing image processing system to meet the storage requirement. Moreover, in the proposed architecture, the computational throughput is well matched to the storage bandwidth, which improve the efficiency of arithmetic processing on the hardware platform. In the experiment, we applied the architecture to the hardware implementation of CNN, and implement on Xilinx ZYNQ xc7z035 platform. Our design is evaluated on a main part of the modified YOLOv2 framework [1]. The experimental results demonstrate that this design can access the off-chip memory efficiently, and can provide the required parameters and input data for the CNN on-chip pipeline processing.
KW - Convolutional Neural Network
KW - FPGA
KW - Image Processing
KW - Memory Access
UR - http://www.scopus.com/inward/record.url?scp=85091952426&partnerID=8YFLogxK
U2 - 10.1109/ICSIDP47821.2019.9173510
DO - 10.1109/ICSIDP47821.2019.9173510
M3 - Conference contribution
AN - SCOPUS:85091952426
T3 - ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019
BT - ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019
Y2 - 11 December 2019 through 13 December 2019
ER -