The Verification System of Sliding Spotlight Mode SAR Imaging based on SoPC

Aiming at the application background of sliding spotlight mode Synthetic Aperture Radar (SAR) imaging processing, this paper builds a System-on-a-Programmable-Chip-based (SoPC-based) sliding spotlight mode SAR imaging verification system, which uses software and hardware collaborative design method to complete algorithm-to-hardware mapping and can quickly and truly perform in FPGA or ASIC. Finally, we analyzed the implementation of the imaging prototype system and the imaging results. For the generation of correlation factors, this paper hierarchically decomposes the factor generation operation to realize the time division multiplexing of the operation unit, in order to reduce resource consumption. At the same time, a variable point Fast Fourier Transformation (FFT) processor based on a variable radix-2³ multiplexing butterfly unit is designed and implemented. Combining these two parts with other modules enables the entire sliding spotlight mode imaging process. On the basis of keeping the error of the result small, the overall resource consumption is greatly reduced. The 102432768 point FFT is implemented by the top-level configurable method, and the operation delay is reduced by more than 20% compared with the Xilinx FFT IP core. The final imaging time is reduced to seconds, and the imaging results meet the requirements. Subsequent compatibility design for other SAR imaging modes also can be achieved.