The implement of spaceborne SAR imaging system

Yan Li, Boya Zhao, Liang Chen*, He Chen, Tao Wang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)

Abstract

With the rapid development of FPGA parallel processing and DSP float-point computing capability, FPGA and DSP play an increasingly important role in the field of high-speed real-time synthetic aperture radar (SAR) signal processing system. In this letter, based on the SAR imaging needs and principles, taking chirp scaling algorithm for example, we design a spaceborne SAR real-time imaging heterogeneous system implemented by FPGA and DSP. The heterogeneous system uses modular thinking, pipeline and parallel processing techniques, which greatly improves the speed and operation precision in SAR imaging. Besides, the SAR imaging system has a good realtime performance, scalability and faulty tolerance and can well meet the needs of spaceborne SAR imaging system. The system needs 19.72s to generate a 4096∗4096 pixel image.

Original languageEnglish
Publication statusPublished - 2015
EventIET International Radar Conference 2015 - Hangzhou, China
Duration: 14 Oct 201516 Oct 2015

Conference

ConferenceIET International Radar Conference 2015
Country/TerritoryChina
CityHangzhou
Period14/10/1516/10/15

Keywords

  • Chirp scaling algorithm
  • Heterogeneous systems
  • Real-time
  • SAR

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