The ASIC design for synthesizing dual channel Gauss white noise

A novel ASIC design for synthesizing Gauss white noise is proposed in this paper. The ASIC design is based on the principle of theoretical analysis and arithmetic iteration which is implemented as pipelined CORDIC architecture. The proposed system not only can generate dual channel Gauss white noise simultaneously, but also consumes similar sources for synthesizing single channel Gauss white noise. The power consumption of this chip is also very low because the chip has an automatic power-down feature. Beside, the goodness and periodicity of Gauss white noise synthesized by ASIC are better than conventional ones so that the ASIC design is especially suited in communication system and radar echo simulation environment etc. The validity of the design is verified by simulation and measurement results.