TADC: Thread-aware divide-and-conquer policy to manage shared cache

Modern Chip Multiprocessors (CMPs) contain multiple cores in a single chip and these cores share last-level cache (LLC). When applications with different memory access behaviors compete for the shared LLC, conventional Least Recently Used (LRU) management policy leads to performance degradation. Applications with different memory access behaviors compete for the shared LLC in different ways, and many researchers have proposed various techniques to improve the performance of the entire CMPs. In this work, we propose a new cache replacement policy (we name it the T ADC) that eliminates the side effects brought by streaming applications and judiciously allocate precious LLC resources to those applications that can benefit from additional cache ways. This new policy equally divides each cache set into several subsets whose number is equal to the number of applications running on the CMPs and maps each subset to each application. It detects the memory access behaviors of different applications in different intervals. And it determines different insertion and promotion policies in different subsets according to their owners' memory access behaviors in the last interval. This new policy can also support inter-core capacity stealing. The proposed T ADC improves the total Instruction Per Cycle (IPC) throughput as much as 24.3% and 5.94% (on average 7.48% and 3.00%) over the baseline LRU policy for Dual-Core workloads and Quad-Core workloads respectively.