Sample-hold amplifier utilizing under-sampling technique

Xing Hua Wang; Shun An Zhong; Lei Zhang

Sample-hold amplifier utilizing under-sampling technique

Xing Hua Wang^*, Shun An Zhong, Lei Zhang

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

This article describes the design and performance of low power under-sampling and hold amplifier used in high speed analog-to-digital converter. The designed circuitry consists of full differential switched capacitor circuit, high speed bootstrapped switch with under-sampling function and two-stage amplifier with continuous common voltage feed-back. The layout of the circuits is plotted under SMIC CMOS 0.18μm 1P6M process with 3.3V supply. The performance of system shows that the SNDR can reach 47dB when the sampling frequency is 2MHz with the power of 1mW and the signal frequency is 2.01MHz (equivalent to 10kHz). The circuit can be widely applied in the FSK system.

Original language	English
Pages (from-to)	822-825
Number of pages	4
Journal	Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology
Volume	30
Issue number	7
Publication status	Published - Jul 2010

Keywords

Full differential circuit
High speed bootstrapped switch
Sampling and hold
Under-sampling

Cite this

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title = "Sample-hold amplifier utilizing under-sampling technique",

abstract = "This article describes the design and performance of low power under-sampling and hold amplifier used in high speed analog-to-digital converter. The designed circuitry consists of full differential switched capacitor circuit, high speed bootstrapped switch with under-sampling function and two-stage amplifier with continuous common voltage feed-back. The layout of the circuits is plotted under SMIC CMOS 0.18μm 1P6M process with 3.3V supply. The performance of system shows that the SNDR can reach 47dB when the sampling frequency is 2MHz with the power of 1mW and the signal frequency is 2.01MHz (equivalent to 10kHz). The circuit can be widely applied in the FSK system.",

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AU - Zhong, Shun An

AU - Zhang, Lei

PY - 2010/7

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N2 - This article describes the design and performance of low power under-sampling and hold amplifier used in high speed analog-to-digital converter. The designed circuitry consists of full differential switched capacitor circuit, high speed bootstrapped switch with under-sampling function and two-stage amplifier with continuous common voltage feed-back. The layout of the circuits is plotted under SMIC CMOS 0.18μm 1P6M process with 3.3V supply. The performance of system shows that the SNDR can reach 47dB when the sampling frequency is 2MHz with the power of 1mW and the signal frequency is 2.01MHz (equivalent to 10kHz). The circuit can be widely applied in the FSK system.

AB - This article describes the design and performance of low power under-sampling and hold amplifier used in high speed analog-to-digital converter. The designed circuitry consists of full differential switched capacitor circuit, high speed bootstrapped switch with under-sampling function and two-stage amplifier with continuous common voltage feed-back. The layout of the circuits is plotted under SMIC CMOS 0.18μm 1P6M process with 3.3V supply. The performance of system shows that the SNDR can reach 47dB when the sampling frequency is 2MHz with the power of 1mW and the signal frequency is 2.01MHz (equivalent to 10kHz). The circuit can be widely applied in the FSK system.

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KW - High speed bootstrapped switch

KW - Sampling and hold

KW - Under-sampling

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JO - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

JF - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

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ER -

Sample-hold amplifier utilizing under-sampling technique

Abstract

Keywords

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