Research on UWB synchronization technology and its implementation in FPGA

Qing Nie; Ning Fang; Zhan Xu; Fei Gao; Bo Yang

doi:10.15918/j.tbit1001-0645.2017.02.012

Research on UWB synchronization technology and its implementation in FPGA

Qing Nie, Ning Fang, Zhan Xu^*, Fei Gao, Bo Yang

^*Corresponding author for this work

School of Information and Electronics

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

In order to simplify the complexity and reduce clock of field programmable gate array(FPGA), an improved multi-channel parallel synchronization scheme was proposed based on traditional sliding window correlation, combining the 1 bit quantification and multipath energy accumulation algorithm. In this paper, a method was designed to implement the FPGA, the influence of 1 bit quantification on system performance was analyzed and the quantitative results of SNR loss was provided. The simulation results show that the 1 bit quantification can bring 2 dB SNR loss in Gaussian and Rayleigh channel. The best threshold range can be got through the simulation of false alarm probability and detection probability in Gaussian and Rayleigh channel.

Original language	English
Pages (from-to)	175-179
Number of pages	5
Journal	Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology
Volume	37
Issue number	2
DOIs	https://doi.org/10.15918/j.tbit1001-0645.2017.02.012
Publication status	Published - 1 Feb 2017

Keywords

1 bit quantification
Gauss channel
Multi-channel parallel
Rayleigh channel
SNR
Synchronous

Access to Document

10.15918/j.tbit1001-0645.2017.02.012

Cite this

@article{57263e3bcde14729869a1b5f5169267f,

title = "Research on UWB synchronization technology and its implementation in FPGA",

abstract = "In order to simplify the complexity and reduce clock of field programmable gate array(FPGA), an improved multi-channel parallel synchronization scheme was proposed based on traditional sliding window correlation, combining the 1 bit quantification and multipath energy accumulation algorithm. In this paper, a method was designed to implement the FPGA, the influence of 1 bit quantification on system performance was analyzed and the quantitative results of SNR loss was provided. The simulation results show that the 1 bit quantification can bring 2 dB SNR loss in Gaussian and Rayleigh channel. The best threshold range can be got through the simulation of false alarm probability and detection probability in Gaussian and Rayleigh channel.",

keywords = "1 bit quantification, Gauss channel, Multi-channel parallel, Rayleigh channel, SNR, Synchronous",

author = "Qing Nie and Ning Fang and Zhan Xu and Fei Gao and Bo Yang",

year = "2017",

month = feb,

day = "1",

doi = "10.15918/j.tbit1001-0645.2017.02.012",

language = "English",

volume = "37",

pages = "175--179",

journal = "Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology",

issn = "1001-0645",

publisher = "Beijing Institute of Technology",

number = "2",

}

TY - JOUR

T1 - Research on UWB synchronization technology and its implementation in FPGA

AU - Nie, Qing

AU - Fang, Ning

AU - Xu, Zhan

AU - Gao, Fei

AU - Yang, Bo

PY - 2017/2/1

Y1 - 2017/2/1

N2 - In order to simplify the complexity and reduce clock of field programmable gate array(FPGA), an improved multi-channel parallel synchronization scheme was proposed based on traditional sliding window correlation, combining the 1 bit quantification and multipath energy accumulation algorithm. In this paper, a method was designed to implement the FPGA, the influence of 1 bit quantification on system performance was analyzed and the quantitative results of SNR loss was provided. The simulation results show that the 1 bit quantification can bring 2 dB SNR loss in Gaussian and Rayleigh channel. The best threshold range can be got through the simulation of false alarm probability and detection probability in Gaussian and Rayleigh channel.

AB - In order to simplify the complexity and reduce clock of field programmable gate array(FPGA), an improved multi-channel parallel synchronization scheme was proposed based on traditional sliding window correlation, combining the 1 bit quantification and multipath energy accumulation algorithm. In this paper, a method was designed to implement the FPGA, the influence of 1 bit quantification on system performance was analyzed and the quantitative results of SNR loss was provided. The simulation results show that the 1 bit quantification can bring 2 dB SNR loss in Gaussian and Rayleigh channel. The best threshold range can be got through the simulation of false alarm probability and detection probability in Gaussian and Rayleigh channel.

KW - 1 bit quantification

KW - Gauss channel

KW - Multi-channel parallel

KW - Rayleigh channel

KW - SNR

KW - Synchronous

UR - http://www.scopus.com/inward/record.url?scp=85018440379&partnerID=8YFLogxK

U2 - 10.15918/j.tbit1001-0645.2017.02.012

DO - 10.15918/j.tbit1001-0645.2017.02.012

M3 - Article

AN - SCOPUS:85018440379

SN - 1001-0645

VL - 37

SP - 175

EP - 179

JO - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

JF - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

IS - 2

ER -

Research on UWB synchronization technology and its implementation in FPGA

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this