Reliability aware simulation flow: From TCAD calibration to circuit level analysis

Razaidi Hussin; Louis Gerrer; Jie Ding; Salvatore Maria Amaroso; Liping Wang; Marco Semicic; Pieter Weckx; Jacopo Franco; Annelies Vanderheyden; Danielle Vanhaeren; Naoto Horiguchi; Ben Kaczer; Asen Asenov

doi:10.1109/SISPAD.2015.7292281

Reliability aware simulation flow: From TCAD calibration to circuit level analysis

Razaidi Hussin, Louis Gerrer, Jie Ding, Salvatore Maria Amaroso, Liping Wang, Marco Semicic, Pieter Weckx, Jacopo Franco, Annelies Vanderheyden, Danielle Vanhaeren, Naoto Horiguchi, Ben Kaczer, Asen Asenov

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Citations (Scopus)

Abstract

In this paper, we present a simulation flow based on TCAD model calibration against experimental transistor measurement and doping profile reverse engineering. Further the physical astatistical variability simulations at TCAD level are also adjusted to match the statistical measurement. This is folloed up by oxide wear out reliability characterization and modelling. Finally statistical compact model libraries for fresh and aged devices are extracted from large samples of TCAD simulation results allowing the performance analysis of a 6T SRAM cell. The calibration procedure has been performed on P and NMOS transistors fabricated and characterized by IMEC, while Glasgow University performed the TCAD reverse engineering and calibration, and the statistical simulations using dedicated Gold Standard Simulations tools.

Original language	English
Title of host publication	2015 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	152-155
Number of pages	4
ISBN (Electronic)	9781467378581
DOIs	https://doi.org/10.1109/SISPAD.2015.7292281
Publication status	Published - 5 Oct 2015
Externally published	Yes
Event	20th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015 - Washington, United States Duration: 9 Sept 2015 → 11 Sept 2015

Publication series

Name	International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume	2015-October

Conference

Conference	20th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015
Country/Territory	United States
City	Washington
Period	9/09/15 → 11/09/15

Keywords

Compact model
Statistical Reliability
Statistical Variability
TCAD simulation
aging

Access to Document

10.1109/SISPAD.2015.7292281

Cite this

Hussin, R., Gerrer, L., Ding, J., Amaroso, S. M., Wang, L., Semicic, M., Weckx, P., Franco, J., Vanderheyden, A., Vanhaeren, D., Horiguchi, N., Kaczer, B., & Asenov, A. (2015). Reliability aware simulation flow: From TCAD calibration to circuit level analysis. In 2015 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015 (pp. 152-155). Article 7292281 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2015-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2015.7292281

Hussin, Razaidi ; Gerrer, Louis ; Ding, Jie et al. / Reliability aware simulation flow : From TCAD calibration to circuit level analysis. 2015 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 152-155 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

@inproceedings{9d1e2bc7984a47fab04ceafe96b00175,

title = "Reliability aware simulation flow: From TCAD calibration to circuit level analysis",

abstract = "In this paper, we present a simulation flow based on TCAD model calibration against experimental transistor measurement and doping profile reverse engineering. Further the physical astatistical variability simulations at TCAD level are also adjusted to match the statistical measurement. This is folloed up by oxide wear out reliability characterization and modelling. Finally statistical compact model libraries for fresh and aged devices are extracted from large samples of TCAD simulation results allowing the performance analysis of a 6T SRAM cell. The calibration procedure has been performed on P and NMOS transistors fabricated and characterized by IMEC, while Glasgow University performed the TCAD reverse engineering and calibration, and the statistical simulations using dedicated Gold Standard Simulations tools.",

keywords = "Compact model, Statistical Reliability, Statistical Variability, TCAD simulation, aging",

author = "Razaidi Hussin and Louis Gerrer and Jie Ding and Amaroso, {Salvatore Maria} and Liping Wang and Marco Semicic and Pieter Weckx and Jacopo Franco and Annelies Vanderheyden and Danielle Vanhaeren and Naoto Horiguchi and Ben Kaczer and Asen Asenov",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 20th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015 ; Conference date: 09-09-2015 Through 11-09-2015",

year = "2015",

month = oct,

day = "5",

doi = "10.1109/SISPAD.2015.7292281",

language = "English",

series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "152--155",

booktitle = "2015 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015",

address = "United States",

}

Hussin, R, Gerrer, L, Ding, J, Amaroso, SM, Wang, L, Semicic, M, Weckx, P, Franco, J, Vanderheyden, A, Vanhaeren, D, Horiguchi, N, Kaczer, B & Asenov, A 2015, Reliability aware simulation flow: From TCAD calibration to circuit level analysis. in 2015 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015., 7292281, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, vol. 2015-October, Institute of Electrical and Electronics Engineers Inc., pp. 152-155, 20th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015, Washington, United States, 9/09/15. https://doi.org/10.1109/SISPAD.2015.7292281

Reliability aware simulation flow: From TCAD calibration to circuit level analysis. / Hussin, Razaidi; Gerrer, Louis; Ding, Jie et al.
2015 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 152-155 7292281 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2015-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Reliability aware simulation flow

T2 - 20th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015

AU - Hussin, Razaidi

AU - Gerrer, Louis

AU - Ding, Jie

AU - Amaroso, Salvatore Maria

AU - Wang, Liping

AU - Semicic, Marco

AU - Weckx, Pieter

AU - Franco, Jacopo

AU - Vanderheyden, Annelies

AU - Vanhaeren, Danielle

AU - Horiguchi, Naoto

AU - Kaczer, Ben

AU - Asenov, Asen

PY - 2015/10/5

Y1 - 2015/10/5

N2 - In this paper, we present a simulation flow based on TCAD model calibration against experimental transistor measurement and doping profile reverse engineering. Further the physical astatistical variability simulations at TCAD level are also adjusted to match the statistical measurement. This is folloed up by oxide wear out reliability characterization and modelling. Finally statistical compact model libraries for fresh and aged devices are extracted from large samples of TCAD simulation results allowing the performance analysis of a 6T SRAM cell. The calibration procedure has been performed on P and NMOS transistors fabricated and characterized by IMEC, while Glasgow University performed the TCAD reverse engineering and calibration, and the statistical simulations using dedicated Gold Standard Simulations tools.

AB - In this paper, we present a simulation flow based on TCAD model calibration against experimental transistor measurement and doping profile reverse engineering. Further the physical astatistical variability simulations at TCAD level are also adjusted to match the statistical measurement. This is folloed up by oxide wear out reliability characterization and modelling. Finally statistical compact model libraries for fresh and aged devices are extracted from large samples of TCAD simulation results allowing the performance analysis of a 6T SRAM cell. The calibration procedure has been performed on P and NMOS transistors fabricated and characterized by IMEC, while Glasgow University performed the TCAD reverse engineering and calibration, and the statistical simulations using dedicated Gold Standard Simulations tools.

KW - Compact model

KW - Statistical Reliability

KW - Statistical Variability

KW - TCAD simulation

KW - aging

UR - http://www.scopus.com/inward/record.url?scp=84959340502&partnerID=8YFLogxK

U2 - 10.1109/SISPAD.2015.7292281

DO - 10.1109/SISPAD.2015.7292281

M3 - Conference contribution

AN - SCOPUS:84959340502

T3 - International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

SP - 152

EP - 155

BT - 2015 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 9 September 2015 through 11 September 2015

ER -

Hussin R, Gerrer L, Ding J, Amaroso SM, Wang L, Semicic M et al. Reliability aware simulation flow: From TCAD calibration to circuit level analysis. In 2015 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 152-155. 7292281. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). doi: 10.1109/SISPAD.2015.7292281

Reliability aware simulation flow: From TCAD calibration to circuit level analysis

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this