Radix-8 FFT processor design based on FPGA

Mingxi Sun; Liyu Tian; Dongmin Dai

doi:10.1109/CISP.2012.6469786

Radix-8 FFT processor design based on FPGA

Mingxi Sun^*, Liyu Tian, Dongmin Dai

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Citations (Scopus)

Abstract

A design of 4096-point radix-8 fast Fourier transform (FFT) is implemented on Field Programming Gate Array (FPGA). The butterfly element, twiddle factor generator, I/O unit have been analyzed and optimized. The processor works in a pipeline style in order to improve the operation speed and reduce the occupancy of the FPGA internal resources. It succeeded in passing the simulation verification and test. The result was compared with Matlab fixed-point model. Under a clock of 100MHz, the processor takes 20.48μs to finish a 4096-point radix-8 FFT, which meets the requirement of high speed digital signal processing.

Original language	English
Title of host publication	2012 5th International Congress on Image and Signal Processing, CISP 2012
Pages	1453-1457
Number of pages	5
DOIs	https://doi.org/10.1109/CISP.2012.6469786
Publication status	Published - 2012
Event	2012 5th International Congress on Image and Signal Processing, CISP 2012 - Chongqing, China Duration: 16 Oct 2012 → 18 Oct 2012

Publication series

Name	2012 5th International Congress on Image and Signal Processing, CISP 2012

Conference

Conference	2012 5th International Congress on Image and Signal Processing, CISP 2012
Country/Territory	China
City	Chongqing
Period	16/10/12 → 18/10/12

Keywords

FFT
FPGA
radix-8
twiddle factor

Access to Document

10.1109/CISP.2012.6469786

Cite this

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title = "Radix-8 FFT processor design based on FPGA",

abstract = "A design of 4096-point radix-8 fast Fourier transform (FFT) is implemented on Field Programming Gate Array (FPGA). The butterfly element, twiddle factor generator, I/O unit have been analyzed and optimized. The processor works in a pipeline style in order to improve the operation speed and reduce the occupancy of the FPGA internal resources. It succeeded in passing the simulation verification and test. The result was compared with Matlab fixed-point model. Under a clock of 100MHz, the processor takes 20.48μs to finish a 4096-point radix-8 FFT, which meets the requirement of high speed digital signal processing.",

keywords = "FFT, FPGA, radix-8, twiddle factor",

author = "Mingxi Sun and Liyu Tian and Dongmin Dai",

year = "2012",

doi = "10.1109/CISP.2012.6469786",

language = "English",

isbn = "9781467309622",

series = "2012 5th International Congress on Image and Signal Processing, CISP 2012",

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note = "2012 5th International Congress on Image and Signal Processing, CISP 2012 ; Conference date: 16-10-2012 Through 18-10-2012",

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Sun, M, Tian, L & Dai, D 2012, Radix-8 FFT processor design based on FPGA. in 2012 5th International Congress on Image and Signal Processing, CISP 2012., 6469786, 2012 5th International Congress on Image and Signal Processing, CISP 2012, pp. 1453-1457, 2012 5th International Congress on Image and Signal Processing, CISP 2012, Chongqing, China, 16/10/12. https://doi.org/10.1109/CISP.2012.6469786

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AU - Tian, Liyu

AU - Dai, Dongmin

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AB - A design of 4096-point radix-8 fast Fourier transform (FFT) is implemented on Field Programming Gate Array (FPGA). The butterfly element, twiddle factor generator, I/O unit have been analyzed and optimized. The processor works in a pipeline style in order to improve the operation speed and reduce the occupancy of the FPGA internal resources. It succeeded in passing the simulation verification and test. The result was compared with Matlab fixed-point model. Under a clock of 100MHz, the processor takes 20.48μs to finish a 4096-point radix-8 FFT, which meets the requirement of high speed digital signal processing.

KW - FFT

KW - FPGA

KW - radix-8

KW - twiddle factor

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Radix-8 FFT processor design based on FPGA

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Keywords

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