Principle of bit-synchronization loop

Ke Sheng, M. R. Anjum, Mussa A. Dida

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)

Abstract

This paper describes the construction and operating principles of bit-synchronization loop study based research, including the principles of the timing-error detector (Gardner Algorithm), the number- controlled oscillator and the interpolation filter. This paper is divided into three parts and simulation results have been performed using MATLAB. At last, the results are analyzed with conclusion that the loop performed the best sampled signal sequences.

Original languageEnglish
Title of host publication17th IEEE International Multi Topic Conference
Subtitle of host publicationCollaborative and Sustainable Development of Technologies, IEEE INMIC 2014 - Proceedings
EditorsHaroon Rasheed, Farah Lakhani, Mukesh Kumar Maheshwari
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages115-118
Number of pages4
ISBN (Electronic)9781479957545
DOIs
Publication statusPublished - 2014
Event17th IEEE International Multi Topic Conference, IEEE INMIC 2014 - Karachi, Pakistan
Duration: 8 Dec 201410 Dec 2014

Publication series

Name17th IEEE International Multi Topic Conference: Collaborative and Sustainable Development of Technologies, IEEE INMIC 2014 - Proceedings

Conference

Conference17th IEEE International Multi Topic Conference, IEEE INMIC 2014
Country/TerritoryPakistan
CityKarachi
Period8/12/1410/12/14

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