Abstract
This paper describes the construction and operating principles of bit-synchronization loop study based research, including the principles of the timing-error detector (Gardner Algorithm), the number- controlled oscillator and the interpolation filter. This paper is divided into three parts and simulation results have been performed using MATLAB. At last, the results are analyzed with conclusion that the loop performed the best sampled signal sequences.
Original language | English |
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Title of host publication | 17th IEEE International Multi Topic Conference |
Subtitle of host publication | Collaborative and Sustainable Development of Technologies, IEEE INMIC 2014 - Proceedings |
Editors | Haroon Rasheed, Farah Lakhani, Mukesh Kumar Maheshwari |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 115-118 |
Number of pages | 4 |
ISBN (Electronic) | 9781479957545 |
DOIs | |
Publication status | Published - 2014 |
Event | 17th IEEE International Multi Topic Conference, IEEE INMIC 2014 - Karachi, Pakistan Duration: 8 Dec 2014 → 10 Dec 2014 |
Publication series
Name | 17th IEEE International Multi Topic Conference: Collaborative and Sustainable Development of Technologies, IEEE INMIC 2014 - Proceedings |
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Conference
Conference | 17th IEEE International Multi Topic Conference, IEEE INMIC 2014 |
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Country/Territory | Pakistan |
City | Karachi |
Period | 8/12/14 → 10/12/14 |
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Sheng, K., Anjum, M. R., & Dida, M. A. (2014). Principle of bit-synchronization loop. In H. Rasheed, F. Lakhani, & M. K. Maheshwari (Eds.), 17th IEEE International Multi Topic Conference: Collaborative and Sustainable Development of Technologies, IEEE INMIC 2014 - Proceedings (pp. 115-118). Article 7097322 (17th IEEE International Multi Topic Conference: Collaborative and Sustainable Development of Technologies, IEEE INMIC 2014 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/INMIC.2014.7097322