Abstract
In this paper, two kinds of optimization techniques were proposed to enhance the performance of H.264 decoder that based on a DSP processor. One approach is to transfer reference data via DMA with a novel approach, which can utilize external bus efficiently. The other approach is to perform the block-based de-blocking filter, which minimizes the times of external memory access. The experimental results show that the proposed solution can improve the H.264 decoding speed by almost 58%. The optimized H.264 decoder can achieve the CIF @25Hz video decoding on a Blackfin 533 processor when operating at 526MHz clock.
| Original language | English |
|---|---|
| Title of host publication | ICSPS 2010 - Proceedings of the 2010 2nd International Conference on Signal Processing Systems |
| Pages | V1649-V1652 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 2010 2nd International Conference on Signal Processing Systems, ICSPS 2010 - Dalian, China Duration: 5 Jul 2010 → 7 Jul 2010 |
Publication series
| Name | ICSPS 2010 - Proceedings of the 2010 2nd International Conference on Signal Processing Systems |
|---|---|
| Volume | 1 |
Conference
| Conference | 2010 2nd International Conference on Signal Processing Systems, ICSPS 2010 |
|---|---|
| Country/Territory | China |
| City | Dalian |
| Period | 5/07/10 → 7/07/10 |
Keywords
- Decoder
- Filter
- H.264
- MC
- Optimization
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Hu, H., & Chen, D. (2010). Optimization techniques for a DSP based H.264 decoder. In ICSPS 2010 - Proceedings of the 2010 2nd International Conference on Signal Processing Systems (pp. V1649-V1652). Article 5555448 (ICSPS 2010 - Proceedings of the 2010 2nd International Conference on Signal Processing Systems; Vol. 1). https://doi.org/10.1109/ICSPS.2010.5555448