Optimization techniques for a DSP based H.264 decoder

Honghua Hu*, Derong Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, two kinds of optimization techniques were proposed to enhance the performance of H.264 decoder that based on a DSP processor. One approach is to transfer reference data via DMA with a novel approach, which can utilize external bus efficiently. The other approach is to perform the block-based de-blocking filter, which minimizes the times of external memory access. The experimental results show that the proposed solution can improve the H.264 decoding speed by almost 58%. The optimized H.264 decoder can achieve the CIF @25Hz video decoding on a Blackfin 533 processor when operating at 526MHz clock.

Original languageEnglish
Title of host publicationICSPS 2010 - Proceedings of the 2010 2nd International Conference on Signal Processing Systems
PagesV1649-V1652
DOIs
Publication statusPublished - 2010
Event2010 2nd International Conference on Signal Processing Systems, ICSPS 2010 - Dalian, China
Duration: 5 Jul 20107 Jul 2010

Publication series

NameICSPS 2010 - Proceedings of the 2010 2nd International Conference on Signal Processing Systems
Volume1

Conference

Conference2010 2nd International Conference on Signal Processing Systems, ICSPS 2010
Country/TerritoryChina
CityDalian
Period5/07/107/07/10

Keywords

  • Decoder
  • Filter
  • H.264
  • MC
  • Optimization

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