New LZW data compression algorithm and its FPGA implementation

Wei Cui

New LZW data compression algorithm and its FPGA implementation

Wei Cui^*

^*Corresponding author for this work

School of Information and Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Citations (Scopus)

Abstract

This paper presents a new LZW data compression algorithm that partitions conventional single large dictionary into a dictionary set that consists of several small address space dictionaries. As doing so the dictionary set not only has small lookup time but also can operate in parallel. Simulation results show that the proposed algorithm has better compression ratio for image data than conventional LZW algorithm and DLZW (dynamic LZW) algorithm, has competitive performance for text data with DLZW algorithm. In addition, a parallel VLSI architecture for implementing the new algorithm is proposed, and it is realized using FPGA XC4VLX15-10. The experiment results show that the chip can yield a compression rate of 198.4 Mbytes/s, it is about 6.9 times the compression rate of implementing conventional LZW, and 3.2 times the compression rate of implementing DLZW.

Original language	English
Title of host publication	PCS 2007 - 26th Picture Coding Symposium
Publication status	Published - 2007
Event	26th Picture Coding Symposium, PCS 2007 - Lisbon, Portugal Duration: 7 Nov 2007 → 9 Nov 2007

Publication series

Name	PCS 2007 - 26th Picture Coding Symposium

Conference

Conference	26th Picture Coding Symposium, PCS 2007
Country/Territory	Portugal
City	Lisbon
Period	7/11/07 → 9/11/07

Keywords

Compression ratio
Dictionary index
Hash function
LZW algorithm
Parallel architecture

Cite this

@inproceedings{456c6bf0affc4cecab9833dfb955bbce,

title = "New LZW data compression algorithm and its FPGA implementation",

abstract = "This paper presents a new LZW data compression algorithm that partitions conventional single large dictionary into a dictionary set that consists of several small address space dictionaries. As doing so the dictionary set not only has small lookup time but also can operate in parallel. Simulation results show that the proposed algorithm has better compression ratio for image data than conventional LZW algorithm and DLZW (dynamic LZW) algorithm, has competitive performance for text data with DLZW algorithm. In addition, a parallel VLSI architecture for implementing the new algorithm is proposed, and it is realized using FPGA XC4VLX15-10. The experiment results show that the chip can yield a compression rate of 198.4 Mbytes/s, it is about 6.9 times the compression rate of implementing conventional LZW, and 3.2 times the compression rate of implementing DLZW.",

keywords = "Compression ratio, Dictionary index, Hash function, LZW algorithm, Parallel architecture",

author = "Wei Cui",

year = "2007",

language = "English",

isbn = "9789898109057",

series = "PCS 2007 - 26th Picture Coding Symposium",

booktitle = "PCS 2007 - 26th Picture Coding Symposium",

note = "26th Picture Coding Symposium, PCS 2007 ; Conference date: 07-11-2007 Through 09-11-2007",

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AU - Cui, Wei

PY - 2007

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N2 - This paper presents a new LZW data compression algorithm that partitions conventional single large dictionary into a dictionary set that consists of several small address space dictionaries. As doing so the dictionary set not only has small lookup time but also can operate in parallel. Simulation results show that the proposed algorithm has better compression ratio for image data than conventional LZW algorithm and DLZW (dynamic LZW) algorithm, has competitive performance for text data with DLZW algorithm. In addition, a parallel VLSI architecture for implementing the new algorithm is proposed, and it is realized using FPGA XC4VLX15-10. The experiment results show that the chip can yield a compression rate of 198.4 Mbytes/s, it is about 6.9 times the compression rate of implementing conventional LZW, and 3.2 times the compression rate of implementing DLZW.

AB - This paper presents a new LZW data compression algorithm that partitions conventional single large dictionary into a dictionary set that consists of several small address space dictionaries. As doing so the dictionary set not only has small lookup time but also can operate in parallel. Simulation results show that the proposed algorithm has better compression ratio for image data than conventional LZW algorithm and DLZW (dynamic LZW) algorithm, has competitive performance for text data with DLZW algorithm. In addition, a parallel VLSI architecture for implementing the new algorithm is proposed, and it is realized using FPGA XC4VLX15-10. The experiment results show that the chip can yield a compression rate of 198.4 Mbytes/s, it is about 6.9 times the compression rate of implementing conventional LZW, and 3.2 times the compression rate of implementing DLZW.

KW - Compression ratio

KW - Dictionary index

KW - Hash function

KW - LZW algorithm

KW - Parallel architecture

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M3 - Conference contribution

AN - SCOPUS:84898067160

SN - 9789898109057

T3 - PCS 2007 - 26th Picture Coding Symposium

BT - PCS 2007 - 26th Picture Coding Symposium

T2 - 26th Picture Coding Symposium, PCS 2007

Y2 - 7 November 2007 through 9 November 2007

ER -

New LZW data compression algorithm and its FPGA implementation

Abstract

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Keywords

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