Multiple regular expression matching hardware architecture

Wei Zhang, Yibo Xue*, Tian Song

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Multiple regular expression matching has become one of the most important performance bottlenecks in network security applications. The paper presents a hardware-based multiple regular expressions matching architecture with a four-stage pipeline. The architecture simultaneously matches multiple regular expressions. The algorithm splits the regular expressions into strings and constrained repetitions and then utilizes a string matching architecture for the strings and a hardware circuit for the constrained repetitions. Experiments show that the architecture can achieve a high throughput of 1.9 Gb/s using Virtex2 devices and 2.1 Gb/s using Virtex4 devices. This solution supports more regular expressions with less storage than other architectures.

Original languageEnglish
Pages (from-to)1704-1707
Number of pages4
JournalQinghua Daxue Xuebao/Journal of Tsinghua University
Volume49
Issue number10
Publication statusPublished - Oct 2009

Keywords

  • Architecture
  • Network security
  • Pattern matching
  • Regular expression matching

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Zhang, W., Xue, Y., & Song, T. (2009). Multiple regular expression matching hardware architecture. Qinghua Daxue Xuebao/Journal of Tsinghua University, 49(10), 1704-1707.