Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

Hong Yu Wang; Hao Fei Wang; Li Xiang Ren; Er Ke Mao

Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

Hong Yu Wang, Hao Fei Wang^*, Li Xiang Ren, Er Ke Mao

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequency synthesizer is based on a direct digital synthesizer (DDS)-driven wideband phase-locked loop (PLL) architecture which can achieve low spurious noise and rapid frequency hopping simultaneously. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor (DAC) output is analyzed. A novel DDS frequency planning method is proposed to ensure low colored noise within the entire bandwidth. The designed output frequency range is 3.765-4.085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range (SFDR) is about 64 dBc in a 320 MHz bandwidth.

Original language	English
Pages (from-to)	514-518
Number of pages	5
Journal	Journal of Beijing Institute of Technology (English Edition)
Volume	22
Issue number	4
Publication status	Published - Dec 2013

Keywords

Direct digital synthesizer (DDS)
Phase-locked loop (PLL)
Spurious components

Cite this

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abstract = "An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequency synthesizer is based on a direct digital synthesizer (DDS)-driven wideband phase-locked loop (PLL) architecture which can achieve low spurious noise and rapid frequency hopping simultaneously. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor (DAC) output is analyzed. A novel DDS frequency planning method is proposed to ensure low colored noise within the entire bandwidth. The designed output frequency range is 3.765-4.085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range (SFDR) is about 64 dBc in a 320 MHz bandwidth.",

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AU - Wang, Hong Yu

AU - Wang, Hao Fei

AU - Ren, Li Xiang

AU - Mao, Er Ke

PY - 2013/12

Y1 - 2013/12

N2 - An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequency synthesizer is based on a direct digital synthesizer (DDS)-driven wideband phase-locked loop (PLL) architecture which can achieve low spurious noise and rapid frequency hopping simultaneously. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor (DAC) output is analyzed. A novel DDS frequency planning method is proposed to ensure low colored noise within the entire bandwidth. The designed output frequency range is 3.765-4.085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range (SFDR) is about 64 dBc in a 320 MHz bandwidth.

AB - An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequency synthesizer is based on a direct digital synthesizer (DDS)-driven wideband phase-locked loop (PLL) architecture which can achieve low spurious noise and rapid frequency hopping simultaneously. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor (DAC) output is analyzed. A novel DDS frequency planning method is proposed to ensure low colored noise within the entire bandwidth. The designed output frequency range is 3.765-4.085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range (SFDR) is about 64 dBc in a 320 MHz bandwidth.

KW - Direct digital synthesizer (DDS)

KW - Phase-locked loop (PLL)

KW - Spurious components

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JF - Journal of Beijing Institute of Technology (English Edition)

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Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

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