Low-latency decoder for quasi-cyclic LDPC codes based on FPGA

Jin Liang Lei; Hong Mei Chen; Ai Hua Wang

Low-latency decoder for quasi-cyclic LDPC codes based on FPGA

Jin Liang Lei, Hong Mei Chen, Ai Hua Wang^*

^*Corresponding author for this work

School of Information and Electronics

Research output: Contribution to journal › Article › peer-review

Abstract

A hardware architecture scheme of low-latency decoder for quasi-cyclic LDPC (QC-LDPC) codes is proposed using Min-Sum decoding algorithm. It takes the advantages of configurable embedded memory in FPGA and pipelining operational mode to improve the throughput of a decoder for QC-LDPC codes. The decoding time complexity is only about 2 times the size of the zoom factor of quasi-cyclic parity check matrix. Compared with non-pipelining decoding structure, the decoding latency is reduced to the original 1/7 without increasing logical resources.

Original language	English
Pages (from-to)	732-735
Number of pages	4
Journal	Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology
Volume	33
Issue number	7
Publication status	Published - Jul 2013

Keywords

FPGA implementation
Low-latency decoder
Pipelining
Quasi-cyclic LDPC

Cite this

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abstract = "A hardware architecture scheme of low-latency decoder for quasi-cyclic LDPC (QC-LDPC) codes is proposed using Min-Sum decoding algorithm. It takes the advantages of configurable embedded memory in FPGA and pipelining operational mode to improve the throughput of a decoder for QC-LDPC codes. The decoding time complexity is only about 2 times the size of the zoom factor of quasi-cyclic parity check matrix. Compared with non-pipelining decoding structure, the decoding latency is reduced to the original 1/7 without increasing logical resources.",

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N2 - A hardware architecture scheme of low-latency decoder for quasi-cyclic LDPC (QC-LDPC) codes is proposed using Min-Sum decoding algorithm. It takes the advantages of configurable embedded memory in FPGA and pipelining operational mode to improve the throughput of a decoder for QC-LDPC codes. The decoding time complexity is only about 2 times the size of the zoom factor of quasi-cyclic parity check matrix. Compared with non-pipelining decoding structure, the decoding latency is reduced to the original 1/7 without increasing logical resources.

AB - A hardware architecture scheme of low-latency decoder for quasi-cyclic LDPC (QC-LDPC) codes is proposed using Min-Sum decoding algorithm. It takes the advantages of configurable embedded memory in FPGA and pipelining operational mode to improve the throughput of a decoder for QC-LDPC codes. The decoding time complexity is only about 2 times the size of the zoom factor of quasi-cyclic parity check matrix. Compared with non-pipelining decoding structure, the decoding latency is reduced to the original 1/7 without increasing logical resources.

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KW - Pipelining

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Low-latency decoder for quasi-cyclic LDPC codes based on FPGA

Abstract

Keywords

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