Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias

Yangyang Yan; Ziyue Zhang; Zhiqiang Cheng; Lingfeng Zhou; Zhiming Chen; Yingtao Ding

doi:10.1109/3DIC.2016.7970040

Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias

Yangyang Yan, Ziyue Zhang, Zhiqiang Cheng, Lingfeng Zhou, Zhiming Chen, Yingtao Ding^*

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

Three-dimensional (3-D) integration with through-silicon-vias(TSVs) has been laid high expectations in overcoming further miniaturization obstacles faced by conventional 2-D integrated circuits (ICs) and solving compatibility problems of system integration among heterogeneous chips. We have proposed a simple but feasible process named 'vacuum-assisted spin coating' for the fabrication of high aspect-ratio TSVs with polyimide (PI) liners at low cost to reduce its parasitic capacitance while increase its thermomechanical reliability. In this paper, the mechanism of the technique, liner thickness controllability, impacts of PI liner on TSV keep-out zone (KOZ), and its adaptability to 'via-last'3-D integration paradigm were addressed. Minimum step coverage of PI liner after the second coating procedure showed an increase from 32.9% to 47.6%, indicating more conformal PI liners were obtained. A 3-D finite element analysis was also employed to check KOZ of TSVs with PI/SiO₂ liners on P-type Si with [100] and [110] device alignment. By employing PI liners, KOZ sizes were seen a reduction of 24.2% and 25.8% on [100] and [110] direction, respectively.

Original language	English
Title of host publication	2016 IEEE International 3D Systems Integration Conference, 3DIC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509013999
DOIs	https://doi.org/10.1109/3DIC.2016.7970040
Publication status	Published - 5 Jul 2017
Event	2016 IEEE International 3D Systems Integration Conference, 3DIC 2016 - San Francisco, United States Duration: 8 Nov 2016 → 11 Nov 2016

Publication series

Name	2016 IEEE International 3D Systems Integration Conference, 3DIC 2016

Conference

Conference	2016 IEEE International 3D Systems Integration Conference, 3DIC 2016
Country/Territory	United States
City	San Francisco
Period	8/11/16 → 11/11/16

Keywords

3-D integration
keep-out-zone(KOZ)
low cost
polyimide liner
through-silicon-vias(TSV)
via-last

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10.1109/3DIC.2016.7970040

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Yan, Y., Zhang, Z., Cheng, Z., Zhou, L., Chen, Z., & Ding, Y. (2017). Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias. In 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016 Article 7970040 (2016 IEEE International 3D Systems Integration Conference, 3DIC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/3DIC.2016.7970040

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title = "Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias",

abstract = "Three-dimensional (3-D) integration with through-silicon-vias(TSVs) has been laid high expectations in overcoming further miniaturization obstacles faced by conventional 2-D integrated circuits (ICs) and solving compatibility problems of system integration among heterogeneous chips. We have proposed a simple but feasible process named 'vacuum-assisted spin coating' for the fabrication of high aspect-ratio TSVs with polyimide (PI) liners at low cost to reduce its parasitic capacitance while increase its thermomechanical reliability. In this paper, the mechanism of the technique, liner thickness controllability, impacts of PI liner on TSV keep-out zone (KOZ), and its adaptability to 'via-last'3-D integration paradigm were addressed. Minimum step coverage of PI liner after the second coating procedure showed an increase from 32.9% to 47.6%, indicating more conformal PI liners were obtained. A 3-D finite element analysis was also employed to check KOZ of TSVs with PI/SiO2 liners on P-type Si with [100] and [110] device alignment. By employing PI liners, KOZ sizes were seen a reduction of 24.2% and 25.8% on [100] and [110] direction, respectively.",

keywords = "3-D integration, keep-out-zone(KOZ), low cost, polyimide liner, through-silicon-vias(TSV), via-last",

author = "Yangyang Yan and Ziyue Zhang and Zhiqiang Cheng and Lingfeng Zhou and Zhiming Chen and Yingtao Ding",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016 ; Conference date: 08-11-2016 Through 11-11-2016",

year = "2017",

month = jul,

day = "5",

doi = "10.1109/3DIC.2016.7970040",

language = "English",

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Yan, Y, Zhang, Z, Cheng, Z, Zhou, L, Chen, Z & Ding, Y 2017, Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias. in 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016., 7970040, 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016, San Francisco, United States, 8/11/16. https://doi.org/10.1109/3DIC.2016.7970040

Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias. / Yan, Yangyang; Zhang, Ziyue; Cheng, Zhiqiang et al.
2016 IEEE International 3D Systems Integration Conference, 3DIC 2016. Institute of Electrical and Electronics Engineers Inc., 2017. 7970040 (2016 IEEE International 3D Systems Integration Conference, 3DIC 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias

AU - Yan, Yangyang

AU - Zhang, Ziyue

AU - Cheng, Zhiqiang

AU - Zhou, Lingfeng

AU - Chen, Zhiming

AU - Ding, Yingtao

PY - 2017/7/5

Y1 - 2017/7/5

N2 - Three-dimensional (3-D) integration with through-silicon-vias(TSVs) has been laid high expectations in overcoming further miniaturization obstacles faced by conventional 2-D integrated circuits (ICs) and solving compatibility problems of system integration among heterogeneous chips. We have proposed a simple but feasible process named 'vacuum-assisted spin coating' for the fabrication of high aspect-ratio TSVs with polyimide (PI) liners at low cost to reduce its parasitic capacitance while increase its thermomechanical reliability. In this paper, the mechanism of the technique, liner thickness controllability, impacts of PI liner on TSV keep-out zone (KOZ), and its adaptability to 'via-last'3-D integration paradigm were addressed. Minimum step coverage of PI liner after the second coating procedure showed an increase from 32.9% to 47.6%, indicating more conformal PI liners were obtained. A 3-D finite element analysis was also employed to check KOZ of TSVs with PI/SiO2 liners on P-type Si with [100] and [110] device alignment. By employing PI liners, KOZ sizes were seen a reduction of 24.2% and 25.8% on [100] and [110] direction, respectively.

AB - Three-dimensional (3-D) integration with through-silicon-vias(TSVs) has been laid high expectations in overcoming further miniaturization obstacles faced by conventional 2-D integrated circuits (ICs) and solving compatibility problems of system integration among heterogeneous chips. We have proposed a simple but feasible process named 'vacuum-assisted spin coating' for the fabrication of high aspect-ratio TSVs with polyimide (PI) liners at low cost to reduce its parasitic capacitance while increase its thermomechanical reliability. In this paper, the mechanism of the technique, liner thickness controllability, impacts of PI liner on TSV keep-out zone (KOZ), and its adaptability to 'via-last'3-D integration paradigm were addressed. Minimum step coverage of PI liner after the second coating procedure showed an increase from 32.9% to 47.6%, indicating more conformal PI liners were obtained. A 3-D finite element analysis was also employed to check KOZ of TSVs with PI/SiO2 liners on P-type Si with [100] and [110] device alignment. By employing PI liners, KOZ sizes were seen a reduction of 24.2% and 25.8% on [100] and [110] direction, respectively.

KW - 3-D integration

KW - keep-out-zone(KOZ)

KW - low cost

KW - polyimide liner

KW - through-silicon-vias(TSV)

KW - via-last

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U2 - 10.1109/3DIC.2016.7970040

DO - 10.1109/3DIC.2016.7970040

M3 - Conference contribution

AN - SCOPUS:85027155694

T3 - 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016

BT - 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016

Y2 - 8 November 2016 through 11 November 2016

ER -

Yan Y, Zhang Z, Cheng Z, Zhou L, Chen Z , Ding Y. Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias. In 2016 IEEE International 3D Systems Integration Conference, 3DIC 2016. Institute of Electrical and Electronics Engineers Inc. 2017. 7970040. (2016 IEEE International 3D Systems Integration Conference, 3DIC 2016). doi: 10.1109/3DIC.2016.7970040

Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias

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