Improving the performance of adaptive cache in reconfigurable VLIW processor

Sensen Hu*, Anthony Brandon, Qi Guo, Yizhuo Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Citations (Scopus)

Abstract

In this paper, we study the impact of cache reconfiguration on the cache misses when the issue-width of a VLIW processor is changed. We clearly note here that our investigation pertains the local temporal effects of the cache resizing and how we counteract the negative impact of cache misses in such resizing instances. We propose a novel reconfigurable d-cache framework that can dynamically adapt its least recently used (LRU) replacement policy without much hardware overhead. We demonstrate that using our adaptive d-cache, it ensures a smooth cache performance from one cache size to the other. This approach is orthogonal to future research in cache resizing for such architectures that take into account energy consumption and performance of the overall application.

Original languageEnglish
Title of host publicationApplied Reconfigurable Computing - 13th International Symposium, ARC 2017, Proceedings
EditorsAntonio Carlos Beck, Luigi Carro , Stephan Wong, Koen Bertels
PublisherSpringer Verlag
Pages3-15
Number of pages13
ISBN (Print)9783319562575
DOIs
Publication statusPublished - 2017
Event13th International Symposium on Applied Reconfigurable Computing, ARC 2017 - Delft, Netherlands
Duration: 3 Apr 20177 Apr 2017

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume10216 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference13th International Symposium on Applied Reconfigurable Computing, ARC 2017
Country/TerritoryNetherlands
City Delft
Period3/04/177/04/17

Keywords

  • Cache
  • Cache resizing
  • Downsizing
  • Issue-width
  • Reconfiguration
  • VLIW
  • ρ-VEX

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