TY - GEN
T1 - IELAS
T2 - 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021
AU - Gao, Tian
AU - Wan, Zishen
AU - Zhang, Yuyang
AU - Yu, Bo
AU - Zhang, Yanjun
AU - Liu, Shaoshan
AU - Raychowdhury, Arijit
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/6/6
Y1 - 2021/6/6
N2 - Stereo matching is a critical task for robot navigation and autonomous vehicles, providing the depth estimation of surroundings. Among all stereo matching algorithms, Efficient Large-scale Stereo (ELAS) offers one of the best tradeoffs between efficiency and accuracy. However, due to the inherent iterative process and unpredictable memory access pattern, ELAS can only run at 1.5-3 fps on high-end CPUs and difficult to achieve real-Time performance on low-power platforms. In this paper, we propose an energy-efficient architecture for real-Time ELAS-based stereo matching on FPGA platform. Moreover, the original computational-intensive and irregular triangulation module is reformed in a regular manner with points interpolation, which is much more hardware-friendly. optimizations, including memory management, parallelism, and pipelining, are further utilized to reduce memory footprint and improve throughput. Compared with Intel i7 CPU and the state-of-The-Art \mathrm{C}\mathrm{P}\mathrm{U}+FPGA implementation, our FPGA realization achieves up to 38.4\times and 3.32\times frame rate improvement, and up to 27.1\times and 1.13\times energy efficiency improvement, respectively.
AB - Stereo matching is a critical task for robot navigation and autonomous vehicles, providing the depth estimation of surroundings. Among all stereo matching algorithms, Efficient Large-scale Stereo (ELAS) offers one of the best tradeoffs between efficiency and accuracy. However, due to the inherent iterative process and unpredictable memory access pattern, ELAS can only run at 1.5-3 fps on high-end CPUs and difficult to achieve real-Time performance on low-power platforms. In this paper, we propose an energy-efficient architecture for real-Time ELAS-based stereo matching on FPGA platform. Moreover, the original computational-intensive and irregular triangulation module is reformed in a regular manner with points interpolation, which is much more hardware-friendly. optimizations, including memory management, parallelism, and pipelining, are further utilized to reduce memory footprint and improve throughput. Compared with Intel i7 CPU and the state-of-The-Art \mathrm{C}\mathrm{P}\mathrm{U}+FPGA implementation, our FPGA realization achieves up to 38.4\times and 3.32\times frame rate improvement, and up to 27.1\times and 1.13\times energy efficiency improvement, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85110022960&partnerID=8YFLogxK
U2 - 10.1109/AICAS51828.2021.9458401
DO - 10.1109/AICAS51828.2021.9458401
M3 - Conference contribution
AN - SCOPUS:85110022960
T3 - 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021
BT - 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 6 June 2021 through 9 June 2021
ER -