Experiences on developing digital down conversion algorithms using xilinx system generator

Chengfa Xu, Yuan Yuan, Lizhi Zhao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The Digital Down Conversion (DDC) algorithm is a classical signal processing method which is widely used in radar and communication systems. In this paper, the DDC function is implemented by Xilinx System Generator tool on FPGA. System Generator is an FPGA design tool provided by Xilinx Inc and MathWorks Inc. It is very convenient for programmers to manipulate the design and debug the function, especially for the complex algorithm. Through the developing process of DDC function based on System Generator, the results show that System Generator is a very fast and efficient tool for FPGA design.

Original languageEnglish
Title of host publicationFifth International Conference on Digital Image Processing, ICDIP 2013
DOIs
Publication statusPublished - 2013
Event5th International Conference on Digital Image Processing, ICDIP 2013 - Beijing, China
Duration: 21 Apr 201322 Apr 2013

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Volume8878
ISSN (Print)0277-786X
ISSN (Electronic)1996-756X

Conference

Conference5th International Conference on Digital Image Processing, ICDIP 2013
Country/TerritoryChina
CityBeijing
Period21/04/1322/04/13

Keywords

  • DDC
  • FPGA
  • System Generator

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