EFFICIENT IMPLEMENTATION OF BP IMAGING ALGORITHM ON FPGA

The Back Projection (BP) imaging algorithm severely affects the efficiency of radar imaging operations due to its high computational complexity. As a parallel processor, Field Programmable Gate Array (FPGA) has significant advantages in parallel data processing. Therefore, this paper uses FPGA as the processing platform to optimize the BP imaging algorithm and shorten data processing time by setting reasonable parallel pipelines, fixed-point floating-point data, and on-chip memory technology. The proposed method validated the data through BP imaging processing and compared it with different methods, verifying the efficiency of the proposed method and achieving a large acceleration ratio, which to some extent improved the imaging processing efficiency.