Dynamic partitioning of scalable cache memory for SMT architectures

The one-level data cache [1], which is optimized for bandwidth, eliminates the overhead to maintain containment and coherence. And it is suitable for future large-scale SMT processor. Although the design has good scalability, large-scale SMT architecture exacerbates the stress on cache, especially for the bank-interleaved data cache referred to in paper [1]. This paper proposes a dynamic partitioning method of scalable cache for large-scale SMT architectures. We extend the scheme proposed in [2] to multi-banking cache. Since memory reference characteristics of threads can change very quickly, our method collects the miss-rate characteristics of simultaneously executing threads at runtime, and partitions the cache among the executing threads. The partitioning scheme has been evaluated using a modified SMT simulator modeling the one-level data cache. The results show a relative improvement in the IPC of up to 18.94% over those generated by the non-partitioned cache using standard least recently used replacement policy.