@inproceedings{cc78d9fc57964ae39c9680bba977f399,
title = "Design of spaceborne SAR imaging processing and fast verification based on FPGA",
abstract = "Realization of real-time processing for spaceborne synthetic aperture radar (SAR) based on FPGA is a tough work because of its complicated algorithm, huge data and difficulty of debugging on board. This paper first analyses the characteristic of FPGA and puts forward fast pulse compression architecture. System-level simulation of FPGA software for spaceborne SAR is carried out by the new way of system verification techniques. According to the hardware environment, system-level simulation model is composed of system input and output, high speed memory interface and DSP interface. Fast debugging for spaceborne SAR imaging software is implemented and its validity has been verified.",
keywords = "FPGA, Pulse compression, Spaceborne SAR, System-level simulation",
author = "Liu Jin and Chen Liang and Liu Ying and Xie Yizhuang",
year = "2013",
doi = "10.1049/cp.2013.0420",
language = "English",
isbn = "9781849196031",
series = "IET Conference Publications",
number = "617 CP",
booktitle = "IET International Radar Conference 2013",
edition = "617 CP",
note = "IET International Radar Conference 2013 ; Conference date: 14-04-2013 Through 16-04-2013",
}