TY - GEN
T1 - Design of quaternary logic circuits based on multiple-valued current mode
AU - Wu, Haixia
AU - Zhong, Shunan
AU - Cai, Qilong
AU - Xia, Qianbin
AU - Chen, Yueyang
PY - 2012
Y1 - 2012
N2 - In order to improve the performance of arithmetic VLSI system, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode (MVCM) by using dynamic source-coupled logic (SCL). Its key components, the comparator and the output generator, are both based on differential-pair circuit (DPC), and the latter is constructed by using structure of DPC trees. The pre-charge evaluates logic style, makes steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source-coupled logic and differential-pair circuit makes its power lower and its structure more compact. The performance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The power dissipation, transistor numbers and delay are superior to corresponding binary CMOS implementation. Multiple-valued logic is the potential solution for the high performance arithmetic VLSI system in the future.
AB - In order to improve the performance of arithmetic VLSI system, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode (MVCM) by using dynamic source-coupled logic (SCL). Its key components, the comparator and the output generator, are both based on differential-pair circuit (DPC), and the latter is constructed by using structure of DPC trees. The pre-charge evaluates logic style, makes steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source-coupled logic and differential-pair circuit makes its power lower and its structure more compact. The performance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The power dissipation, transistor numbers and delay are superior to corresponding binary CMOS implementation. Multiple-valued logic is the potential solution for the high performance arithmetic VLSI system in the future.
KW - Multiple-valued current mode
KW - Multiple-valued logic
KW - SCL circuit
UR - http://www.scopus.com/inward/record.url?scp=84859175340&partnerID=8YFLogxK
U2 - 10.1007/978-1-4471-2467-2_56
DO - 10.1007/978-1-4471-2467-2_56
M3 - Conference contribution
AN - SCOPUS:84859175340
SN - 9781447124665
T3 - Lecture Notes in Electrical Engineering
SP - 479
EP - 488
BT - Electrical, Information Engineering and Mechatronics 2011 - Proceedings of the 2011 International Conference on Electrical, Information Engineering and Mechatronics, EIEM 2011
T2 - 2011 International Conference on Electrical, Information Engineering and Mechatronics, EIEM 2011
Y2 - 23 December 2011 through 25 December 2011
ER -