Design of on-chip clock generation with 50/50 duty cycle correction

Wei Cui; H. Chen; Yueqiu Han

Design of on-chip clock generation with 50/50 duty cycle correction

Wei Cui^*, H. Chen, Yueqiu Han

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

A circuit design of on-chip clock generation which improves the duty cycle performance and prevents latch-up effect is described. The circuit provides on-chip clock with automatic duty cycle correction so as to overcome the shortcoming of clock duty cycle dependence on technology parameters of the traditional on-chip clock generation circuit. It is extremely important that the dynamic power consumption equals approximately the one of its predecessor. The effective performance of the proposed circuit is confirmed by SPICE simulation.

Original language	English
Pages (from-to)	144-146
Number of pages	3
Journal	Chinese Journal of Electronics
Volume	12
Issue number	1
Publication status	Published - Jan 2003

Keywords

2 divided-frequency
Astable multivibrator
Clock generation
Duty cycle
Latch-up effect

Cite this

Cui, W., Chen, H., & Han, Y. (2003). Design of on-chip clock generation with 50/50 duty cycle correction. Chinese Journal of Electronics, 12(1), 144-146.

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Design of on-chip clock generation with 50/50 duty cycle correction

Abstract

Keywords

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