Design of on-chip clock generation with 50/50 duty cycle correction

A circuit design of on-chip clock generation which improves the duty cycle performance and prevents latch-up effect is described. The circuit provides on-chip clock with automatic duty cycle correction so as to overcome the shortcoming of clock duty cycle dependence on technology parameters of the traditional on-chip clock generation circuit. It is extremely important that the dynamic power consumption equals approximately the one of its predecessor. The effective performance of the proposed circuit is confirmed by SPICE simulation.