TY - GEN
T1 - Design of new intelligent redundant serial bus with isolated driver in the distributed control system
AU - Wang, Ling
AU - Mo, Bo
AU - Li, Qing Hua
AU - Mei, Hong
PY - 2014
Y1 - 2014
N2 - In the distributed control system, to make sure the running of the system bus is long-term, stable and reliable, we design a new intelligent redundant serial bus as the system bus, and it will be introduced in this article. The new intelligent redundant serial bus (IRSBUS) is able to be configured into a dual redundant synchronous bus or a quadruple redundant asynchronous bus, and its redundancy is "hot" redundant that means two groups of the four signals are working together. We mainly design a redundant IP core, a redundant protocol and the byte format. The IP core of IRSBUS consists of the following major modules: Intelligent Signal Router, Signal Transceiver, Lines-connecting Status Detector, Synchronous Controller (Master), Synchronous Transponder (Slave), Redundant Results Decider, Interrupt Generator, Dual-port RAMs, Control and Status Registers, Master/Slave Redundant Logical Controller. The redundant protocol and byte format provide an extremely strict timing to synchronize the master-slaves and transmit the information. We show that our design allow to compare the redundant data to arrive at the correct results. It also provides a way to regroup the remaining signal lines into a system bus when one or two of the four signal lines are broken. And then it detects the lines-connection status every 100 milliseconds.
AB - In the distributed control system, to make sure the running of the system bus is long-term, stable and reliable, we design a new intelligent redundant serial bus as the system bus, and it will be introduced in this article. The new intelligent redundant serial bus (IRSBUS) is able to be configured into a dual redundant synchronous bus or a quadruple redundant asynchronous bus, and its redundancy is "hot" redundant that means two groups of the four signals are working together. We mainly design a redundant IP core, a redundant protocol and the byte format. The IP core of IRSBUS consists of the following major modules: Intelligent Signal Router, Signal Transceiver, Lines-connecting Status Detector, Synchronous Controller (Master), Synchronous Transponder (Slave), Redundant Results Decider, Interrupt Generator, Dual-port RAMs, Control and Status Registers, Master/Slave Redundant Logical Controller. The redundant protocol and byte format provide an extremely strict timing to synchronize the master-slaves and transmit the information. We show that our design allow to compare the redundant data to arrive at the correct results. It also provides a way to regroup the remaining signal lines into a system bus when one or two of the four signal lines are broken. And then it detects the lines-connection status every 100 milliseconds.
KW - Distributed control system
KW - Dual redundant synchronous bus
KW - IP core
KW - Intelligent
KW - Quadruple redundant asynchronous bus
KW - Redundant protocol
UR - http://www.scopus.com/inward/record.url?scp=84896874094&partnerID=8YFLogxK
U2 - 10.4028/www.scientific.net/AMM.527.242
DO - 10.4028/www.scientific.net/AMM.527.242
M3 - Conference contribution
AN - SCOPUS:84896874094
SN - 9783038350293
T3 - Applied Mechanics and Materials
SP - 242
EP - 247
BT - Mechatronics and Computational Mechanics II
T2 - 2013 2nd International Conference on Mechatronics and Computational Mechanics, ICMCM 2013
Y2 - 30 December 2013 through 31 December 2013
ER -