TY - GEN
T1 - Design of a low-power-consumption and high-performance sigma-delta modulator
AU - Chen, Yueyang
AU - Zhong, Shun'an
AU - Dang, Hua
PY - 2009
Y1 - 2009
N2 - Based on the switched-capacitor discrete time sampling technique in 0.18μm CMOS technology, a modified single loop 3rd order sigma-delta modulator used for a resolution of 16bit sigma-delta ADC was proposed. The analysis of sigma-delta modulator structures and the design flow were given. The method to design NTF and the principle to determine the index of circuit module were also introduced. The modulator is proved to be robustness, the high performance in stability, anti-mismatch, chip area, and the power consumption is only 2.6mw when the power supply is 2.8V.
AB - Based on the switched-capacitor discrete time sampling technique in 0.18μm CMOS technology, a modified single loop 3rd order sigma-delta modulator used for a resolution of 16bit sigma-delta ADC was proposed. The analysis of sigma-delta modulator structures and the design flow were given. The method to design NTF and the principle to determine the index of circuit module were also introduced. The modulator is proved to be robustness, the high performance in stability, anti-mismatch, chip area, and the power consumption is only 2.6mw when the power supply is 2.8V.
KW - Index of circuit module
KW - Sigma-delta modulators
KW - Structure of modulators
UR - http://www.scopus.com/inward/record.url?scp=70449089558&partnerID=8YFLogxK
U2 - 10.1109/CSIE.2009.772
DO - 10.1109/CSIE.2009.772
M3 - Conference contribution
AN - SCOPUS:70449089558
SN - 9780769535074
T3 - 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
SP - 375
EP - 379
BT - 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
T2 - 2009 WRI World Congress on Computer Science and Information Engineering, CSIE 2009
Y2 - 31 March 2009 through 2 April 2009
ER -