Design of a 2.5Gbps clock-data recovery circuit in 0.18um standard CMOS process

Yueyang Chen; Shun'an Zhong; Hua Dang

doi:10.1109/ASICON.2009.5351164

Design of a 2.5Gbps clock-data recovery circuit in 0.18um standard CMOS process

Yueyang Chen^*, Shun'an Zhong, Hua Dang

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A 2.5Gbps Clock-Data Recovery (CDR) circuit is designed in 0.18um standard CMOS process in this work. The CDR circuit utilizes one PLL loop and one CMU loop. The CDR loop works at 2.5GHz by SONET OC-48 while the CMU loop runs at 625MHz. The power consumption is 25mW. The jitter bandwidth is 5.6MHz. The peaking is 2.67dB. The VCO gain is 163MHz/V with a tuning range of 390MHz. The output data and clock amplitude is 500mV SEPP (single-ended peak to peak). Random Jitter is 0.1mUI rms and the output data ISI is 10mUI.

Original language	English
Title of host publication	ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages	1153-1156
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2009.5351164
Publication status	Published - 2009
Event	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China Duration: 20 Oct 2009 → 23 Oct 2009

Publication series

Name	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Conference

Conference	2009 8th IEEE International Conference on ASIC, ASICON 2009
Country/Territory	China
City	Changsha
Period	20/10/09 → 23/10/09

Keywords

CDR
CMOS
CMU
High-speed
PLL

Access to Document

10.1109/ASICON.2009.5351164

Cite this

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title = "Design of a 2.5Gbps clock-data recovery circuit in 0.18um standard CMOS process",

abstract = "A 2.5Gbps Clock-Data Recovery (CDR) circuit is designed in 0.18um standard CMOS process in this work. The CDR circuit utilizes one PLL loop and one CMU loop. The CDR loop works at 2.5GHz by SONET OC-48 while the CMU loop runs at 625MHz. The power consumption is 25mW. The jitter bandwidth is 5.6MHz. The peaking is 2.67dB. The VCO gain is 163MHz/V with a tuning range of 390MHz. The output data and clock amplitude is 500mV SEPP (single-ended peak to peak). Random Jitter is 0.1mUI rms and the output data ISI is 10mUI.",

keywords = "CDR, CMOS, CMU, High-speed, PLL",

author = "Yueyang Chen and Shun'an Zhong and Hua Dang",

year = "2009",

doi = "10.1109/ASICON.2009.5351164",

language = "English",

isbn = "9781424438686",

series = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",

pages = "1153--1156",

booktitle = "ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC",

note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",

}

Chen, Y, Zhong, S & Dang, H 2009, Design of a 2.5Gbps clock-data recovery circuit in 0.18um standard CMOS process. in ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC., 5351164, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, pp. 1153-1156, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, China, 20/10/09. https://doi.org/10.1109/ASICON.2009.5351164

Design of a 2.5Gbps clock-data recovery circuit in 0.18um standard CMOS process. / Chen, Yueyang; Zhong, Shun'an; Dang, Hua.
ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. p. 1153-1156 5351164 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A 2.5Gbps Clock-Data Recovery (CDR) circuit is designed in 0.18um standard CMOS process in this work. The CDR circuit utilizes one PLL loop and one CMU loop. The CDR loop works at 2.5GHz by SONET OC-48 while the CMU loop runs at 625MHz. The power consumption is 25mW. The jitter bandwidth is 5.6MHz. The peaking is 2.67dB. The VCO gain is 163MHz/V with a tuning range of 390MHz. The output data and clock amplitude is 500mV SEPP (single-ended peak to peak). Random Jitter is 0.1mUI rms and the output data ISI is 10mUI.

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Design of a 2.5Gbps clock-data recovery circuit in 0.18um standard CMOS process

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Keywords

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