Design and optimization on reconfigurable butterfly core for a real-time FFT processor

Zhizhe Liu, Shunan Zhong, Yueyang Chen*, Weinan Chu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Runtime reconfigurable FFT processors on scale of data frame samples are being concerned and designed A novel solution based on the reusable butterfly core is proposed for achievement of reconfigurable FFT processors. An alternative mixed fabric in radix-4 and radix-2 is applied to the proposed butterfly core. Parallel in-place memory access rule is proposed to fulfill the range of data frame sample scale, from 1024 to 16, with the recursive architecture of the single butterfly core. Implementation of the proposed FFT processor is under the technology of SMIC 0.18μm CMOS, which gets to 3 ns on critical path and 2 mm2 of a core area by reason of the optimization solution on data paths with 4-2 compressor clusters, instead of regular adders, and on data A, which is the data without rotation in the dragonfly core, with preprocessing.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages847-850
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
Duration: 20 Oct 200923 Oct 2009

Publication series

NameASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Conference

Conference2009 8th IEEE International Conference on ASIC, ASICON 2009
Country/TerritoryChina
CityChangsha
Period20/10/0923/10/09

Keywords

  • Radix-2
  • Radix-4
  • Reconfigurable butterfly core
  • Runtime configurable FFT

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