Abstract
On the basis of analyzing existing butterfly designs, an efficient design method of pipeline single precision floating-point butterfly unit for radix-3 fast Fourier transform (FFT) is proposed. First, a simplified radix-3 butterfly model is established using the Cooley-Tukey algorithm; then, with the introducing of the constant integer multiplication, 3-point discrete Fourier transform (DFT) matrix floating-point complex multiplication is realized using finite fix-point additions. Combined with classic floating-point multiplication and addition unit, the radix-3 butterfly unit is deduced. Compared with conventional designs, the proposed design reduces floating-point operations and saves hardware resources. Simulation experiments and engineering application results show that, the proposed design method can meet the precision requirement of the system while ensuring real-time computing capability compared to other hardware or software implementation.
Original language | English |
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Pages (from-to) | 2675-2681 |
Number of pages | 7 |
Journal | Yi Qi Yi Biao Xue Bao/Chinese Journal of Scientific Instrument |
Volume | 31 |
Issue number | 12 |
Publication status | Published - Dec 2010 |
Keywords
- Butterfly-computing
- CSD
- FPGA
- Single precision floating-point