TY - GEN
T1 - Communication locality analysis of triplet-based hierarchical interconnection network in chip multiprocessor
AU - Talpur, Shahnawaz
AU - Shi, Feng
AU - Wang, Yizhuo
PY - 2012
Y1 - 2012
N2 - Interconnection topology inside chip multiprocessor acts as fundamental role in communication locality. Considering compiler optimization data locality has been an inmost hypothesis in the high performance computing. Conversely, data locality sphere has several troubles when its degree of dimension is two or higher. In mesh network of two dimensions, each core is connected with its four neighbors. The data locality can potentially be exploited in two dimensions considering the specified processor's perspective. A Triplet-Based Hierarchical Interconnection Network (TBHIN) has straightforward topology and fractal attribute for chip multiprocessor. In this paper, a static (no contention) performance analysis of TBHIN and 2-D mesh is presented, based on the premise of locality in communication. The dynamic (contention) software simulation of TBHIN shows that the stronger the locality in communication, the lower the delay of the communication.
AB - Interconnection topology inside chip multiprocessor acts as fundamental role in communication locality. Considering compiler optimization data locality has been an inmost hypothesis in the high performance computing. Conversely, data locality sphere has several troubles when its degree of dimension is two or higher. In mesh network of two dimensions, each core is connected with its four neighbors. The data locality can potentially be exploited in two dimensions considering the specified processor's perspective. A Triplet-Based Hierarchical Interconnection Network (TBHIN) has straightforward topology and fractal attribute for chip multiprocessor. In this paper, a static (no contention) performance analysis of TBHIN and 2-D mesh is presented, based on the premise of locality in communication. The dynamic (contention) software simulation of TBHIN shows that the stronger the locality in communication, the lower the delay of the communication.
KW - Chip multiprocessor
KW - Communication locality
KW - Interconnection network
KW - Mesh
UR - http://www.scopus.com/inward/record.url?scp=84871583823&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-35606-3_4
DO - 10.1007/978-3-642-35606-3_4
M3 - Conference contribution
AN - SCOPUS:84871583823
SN - 9783642356056
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 33
EP - 41
BT - Network and Parallel Computing - 9th IFIP International Conference, NPC 2012, Proceedings
T2 - 9th IFIP International Conference on Network and Parallel Computing, NPC 2012
Y2 - 6 September 2012 through 8 September 2012
ER -