Circuit noise effect on sampling clock in frequency-domain radio receiver IF digitization

Lei Sun*, Miao Yang, Ronghua Zhou, Jianping An, Zhijun Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Quantization of the coefficients obtained by the projection of a continuous time signal over an orthogonal space is proposed recently as a new analog to digital (A/D) converting solution. The new A/D technique is to sample the input signal in orthogonal domains which may lead to reduce the degree of signal distortion and significantly less demanding A/D conversion characteristics. As a particular case, the frequency domain analog to digital converter (ADC) overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. Analytical expressions for the A/D conversion with clock jitter error are developed. The computer simulations are presented to show the relationship between sampling clock jitter and A/D conversion performance.

Original languageEnglish
Title of host publicationProceedings - 5th International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2009
DOIs
Publication statusPublished - 2009
Event5th International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2009 - Beijing, China
Duration: 24 Sept 200926 Sept 2009

Publication series

NameProceedings - 5th International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2009

Conference

Conference5th International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2009
Country/TerritoryChina
CityBeijing
Period24/09/0926/09/09

Keywords

  • Analog to digital conversion in the frequency domain
  • Clock jitter
  • Crosstalk
  • Signal-to-noise ratio

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