Automatic synthesizable HDL generator for NoGAP

Wenbiao Zhou*, Per Karlström, Dake Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

ASIP are needed to handle the future demand of flexible yet high performance computation in mobile devices. However designing an ASIP is complicated by the fact that not only the processor, but also tools such as assemblers, simulators, and compilers have to be designed. NoGAP is a design automation tool for ASIP design that imposes very few limitations on the designer. Yet NoGAP supports the designer by automating much of the tedious and error prone tasks associated with ASIP design. This paper presented the methodology to fully generate a synthesizable HDL from NoGAP CL description in NoGAP system. The advantage of NoGAP is that it is a unify process without any architecture restriction. The case study shows NoGAP can successfully generate ASIP's HDL description and the hardware generated by NoGAP does not incur any performance loss than manually handled design.

Original languageEnglish
Title of host publicationProceedings - 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, ICIS 2012
Pages119-123
Number of pages5
DOIs
Publication statusPublished - 2012
Event2012 IEEE/ACIS 11th International Conference on Computer and Information Science, ICIS 2012 - Shanghai, China
Duration: 30 May 20121 Jun 2012

Publication series

NameProceedings - 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, ICIS 2012

Conference

Conference2012 IEEE/ACIS 11th International Conference on Computer and Information Science, ICIS 2012
Country/TerritoryChina
CityShanghai
Period30/05/121/06/12

Keywords

  • ADL
  • ASIP
  • CAD
  • HDL

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