TY - GEN
T1 - An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS Technology
AU - Zhu, Wei
AU - Wang, Ruitao
AU - Zhang, Jian
AU - Wang, Jiawen
AU - Li, Chenguang
AU - Wang, Yan
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This paper presents a bidirectional 25.8-39.2GHz phased-array transceiver front-end for 5G in a 65nm CMOS. An efficient T/R folding architecture is proposed, so that the whole transmit(TX) and the receive (RX) paths can be folded together and share footprints to greatly improve the area efficiency with negligible performance penalty. The RX path also can be reused as TX power detection/self-calibration path in TX mode. Broadband transformer-based T/R switching, attenuation and phase-shifting techniques are also introduced to realize broadband beamforming and maintain high area efficiency. The protype achieves measured >25.8-39.2GHz bandwidth in both TX and RX modes. It also supports 64-/256-/512-QAM at 28/39GHz bands for 5G with the core area of 0.195mm2 that is only 25 to 40% of the size occupied in prior work.
AB - This paper presents a bidirectional 25.8-39.2GHz phased-array transceiver front-end for 5G in a 65nm CMOS. An efficient T/R folding architecture is proposed, so that the whole transmit(TX) and the receive (RX) paths can be folded together and share footprints to greatly improve the area efficiency with negligible performance penalty. The RX path also can be reused as TX power detection/self-calibration path in TX mode. Broadband transformer-based T/R switching, attenuation and phase-shifting techniques are also introduced to realize broadband beamforming and maintain high area efficiency. The protype achieves measured >25.8-39.2GHz bandwidth in both TX and RX modes. It also supports 64-/256-/512-QAM at 28/39GHz bands for 5G with the core area of 0.195mm2 that is only 25 to 40% of the size occupied in prior work.
UR - http://www.scopus.com/inward/record.url?scp=85135228872&partnerID=8YFLogxK
U2 - 10.1109/VLSITechnologyandCir46769.2022.9830312
DO - 10.1109/VLSITechnologyandCir46769.2022.9830312
M3 - Conference contribution
AN - SCOPUS:85135228872
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 102
EP - 103
BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Y2 - 12 June 2022 through 17 June 2022
ER -