An optimized design of under-sampling 100MHz-10b time-interleaved pipelined ADC

Xinghua Wang; Shun'an Zhong; Zhang Zhuo

doi:10.1109/ICCET.2010.5485889

An optimized design of under-sampling 100MHz-10b time-interleaved pipelined ADC

Xinghua Wang^*, Shun'an Zhong, Zhang Zhuo

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An under-sampling high speed pipelined ADC is proposed with optimized two-channel time-interleaved architecture. The two channels have a common SHA which is designed for under-sampling while the clock frequency in each channel is half of it in SHA. And in the two-channel time-interleaved pipelined part, the shared operational amplifier compensates for the large mismatch between the channels in each same stage. This design minimizes power consumption and chip area in time-interleaved ADC. Under SMIC 0.35um 1P6M process with 3.3V supply, the performance of SNR reaches nearly 65dB with the condition that the sampling rate is 100MHz and the input frequency is scanned from 1MHz to 110MHz. The current consumption of 100MSps is about 34mA.

Original language	English
Title of host publication	ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings
Pages	V3383-V3386
DOIs	https://doi.org/10.1109/ICCET.2010.5485889
Publication status	Published - 2010
Event	2010 2nd International Conference on Computer Engineering and Technology, ICCET 2010 - Chengdu, China Duration: 16 Apr 2010 → 18 Apr 2010

Publication series

Name	ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings
Volume	3

Conference

Conference	2010 2nd International Conference on Computer Engineering and Technology, ICCET 2010
Country/Territory	China
City	Chengdu
Period	16/04/10 → 18/04/10

Keywords

Bootstrapped switch
Shared amplifier
Time interleaved
Under sampling

Access to Document

10.1109/ICCET.2010.5485889

Cite this

Wang, X., Zhong, S., & Zhuo, Z. (2010). An optimized design of under-sampling 100MHz-10b time-interleaved pipelined ADC. In ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings (pp. V3383-V3386). Article 5485889 (ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings; Vol. 3). https://doi.org/10.1109/ICCET.2010.5485889

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title = "An optimized design of under-sampling 100MHz-10b time-interleaved pipelined ADC",

abstract = "An under-sampling high speed pipelined ADC is proposed with optimized two-channel time-interleaved architecture. The two channels have a common SHA which is designed for under-sampling while the clock frequency in each channel is half of it in SHA. And in the two-channel time-interleaved pipelined part, the shared operational amplifier compensates for the large mismatch between the channels in each same stage. This design minimizes power consumption and chip area in time-interleaved ADC. Under SMIC 0.35um 1P6M process with 3.3V supply, the performance of SNR reaches nearly 65dB with the condition that the sampling rate is 100MHz and the input frequency is scanned from 1MHz to 110MHz. The current consumption of 100MSps is about 34mA.",

keywords = "Bootstrapped switch, Shared amplifier, Time interleaved, Under sampling",

author = "Xinghua Wang and Shun'an Zhong and Zhang Zhuo",

year = "2010",

doi = "10.1109/ICCET.2010.5485889",

language = "English",

isbn = "9781424463503",

series = "ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings",

pages = "V3383--V3386",

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note = "2010 2nd International Conference on Computer Engineering and Technology, ICCET 2010 ; Conference date: 16-04-2010 Through 18-04-2010",

}

Wang, X, Zhong, S & Zhuo, Z 2010, An optimized design of under-sampling 100MHz-10b time-interleaved pipelined ADC. in ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings., 5485889, ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings, vol. 3, pp. V3383-V3386, 2010 2nd International Conference on Computer Engineering and Technology, ICCET 2010, Chengdu, China, 16/04/10. https://doi.org/10.1109/ICCET.2010.5485889

An optimized design of under-sampling 100MHz-10b time-interleaved pipelined ADC. / Wang, Xinghua; Zhong, Shun'an; Zhuo, Zhang.
ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings. 2010. p. V3383-V3386 5485889 (ICCET 2010 - 2010 International Conference on Computer Engineering and Technology, Proceedings; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - An under-sampling high speed pipelined ADC is proposed with optimized two-channel time-interleaved architecture. The two channels have a common SHA which is designed for under-sampling while the clock frequency in each channel is half of it in SHA. And in the two-channel time-interleaved pipelined part, the shared operational amplifier compensates for the large mismatch between the channels in each same stage. This design minimizes power consumption and chip area in time-interleaved ADC. Under SMIC 0.35um 1P6M process with 3.3V supply, the performance of SNR reaches nearly 65dB with the condition that the sampling rate is 100MHz and the input frequency is scanned from 1MHz to 110MHz. The current consumption of 100MSps is about 34mA.

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An optimized design of under-sampling 100MHz-10b time-interleaved pipelined ADC

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