@inproceedings{d5541ccc555a4e0ca96026a5c848ddcb,
title = "An analytical model for capacitance of silicon-insulator-silicon through-silicon-vias",
abstract = "In order to achieve a minimum and stable TSV capacitance independent of operating voltage and frequency, a simple but feasible silicon-insulator-silicon (SIS) TSV structure is proposed using ultra-low-resistivity silicon (ULRS) and polymer Benzocyclobutene (BCB). In this paper, an analytical model for capacitance evaluation of the proposed SIS TSV is strictly derived in detail from Poisson's equation and physics of semiconductor. The analytical model shows a good agreement with both 3D full-wave electromagnetic simulation and on-wafer measurement within a wide frequency range up to 50 GHz. Constant C-and C-V characteristics as well as wafer-level uniformity and geometric verification are also demonstrated.",
keywords = "capacitance, modeling, silicon-insulator-silicon (SIS), through-silicon-via (TSV)",
author = "Bohao Li and An'An Li and Miao Xiong and Jianxun Yang and Zhiming Chen and Yingtao Ding",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 17th International Conference on Electronic Packaging Technology, ICEPT 2016 ; Conference date: 16-08-2016 Through 19-08-2016",
year = "2016",
month = oct,
day = "4",
doi = "10.1109/ICEPT.2016.7583400",
language = "English",
series = "2016 17th International Conference on Electronic Packaging Technology, ICEPT 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1464--1468",
editor = "Keyun Bi and Sheng Liu and Shengjun Zhou",
booktitle = "2016 17th International Conference on Electronic Packaging Technology, ICEPT 2016",
address = "United States",
}