An 8-bit 80MS/s 2b/cycle SAR ADC for Sensor Application

Lei Zhang; Wenzhong Lou; Yige Gao

doi:10.1109/ISAPE.2018.8634360

An 8-bit 80MS/s 2b/cycle SAR ADC for Sensor Application

Lei Zhang, Wenzhong Lou, Yige Gao

School of Mechatronical Engineering

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

This paper presents an 8-bit, 80MS/s Successive Approximation Register analog-to-digital converter (SAR ADC) with 2bit/cycle structure for sensor application. By using two capacitor-DAC arrays, S-DAC and R-DAC, the proposed SAR ADC can obtain 2-bit in one comparison cycle. With split-capacitor structure and monotonic switching strategy, two DACs reduce the number of capacitors and save the ADC power consumption. The proposed asynchronous control logic speeds up the ADC. The proposed ADC achieves 46.17dB SNDR at 80MS/s rate with 1.8V supply voltage in 180nm CMOS process.

Original language	English
Title of host publication	2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538673027
DOIs	https://doi.org/10.1109/ISAPE.2018.8634360
Publication status	Published - 2 Jul 2018
Event	12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Hangzhou, China Duration: 3 Dec 2018 → 6 Dec 2018

Publication series

Name	2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings

Conference

Conference	12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018
Country/Territory	China
City	Hangzhou
Period	3/12/18 → 6/12/18

Keywords

2b/cycle
SAR ADC
analog-to-digital converter
split-capacitor

Access to Document

10.1109/ISAPE.2018.8634360

Cite this

Zhang, L., Lou, W., & Gao, Y. (2018). An 8-bit 80MS/s 2b/cycle SAR ADC for Sensor Application. In 2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings Article 8634360 (2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISAPE.2018.8634360

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abstract = "This paper presents an 8-bit, 80MS/s Successive Approximation Register analog-to-digital converter (SAR ADC) with 2bit/cycle structure for sensor application. By using two capacitor-DAC arrays, S-DAC and R-DAC, the proposed SAR ADC can obtain 2-bit in one comparison cycle. With split-capacitor structure and monotonic switching strategy, two DACs reduce the number of capacitors and save the ADC power consumption. The proposed asynchronous control logic speeds up the ADC. The proposed ADC achieves 46.17dB SNDR at 80MS/s rate with 1.8V supply voltage in 180nm CMOS process.",

keywords = "2b/cycle, SAR ADC, analog-to-digital converter, split-capacitor",

author = "Lei Zhang and Wenzhong Lou and Yige Gao",

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Zhang, L, Lou, W & Gao, Y 2018, An 8-bit 80MS/s 2b/cycle SAR ADC for Sensor Application. in 2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings., 8634360, 2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018, Hangzhou, China, 3/12/18. https://doi.org/10.1109/ISAPE.2018.8634360

An 8-bit 80MS/s 2b/cycle SAR ADC for Sensor Application. / Zhang, Lei; Lou, Wenzhong; Gao, Yige.
2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8634360 (2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents an 8-bit, 80MS/s Successive Approximation Register analog-to-digital converter (SAR ADC) with 2bit/cycle structure for sensor application. By using two capacitor-DAC arrays, S-DAC and R-DAC, the proposed SAR ADC can obtain 2-bit in one comparison cycle. With split-capacitor structure and monotonic switching strategy, two DACs reduce the number of capacitors and save the ADC power consumption. The proposed asynchronous control logic speeds up the ADC. The proposed ADC achieves 46.17dB SNDR at 80MS/s rate with 1.8V supply voltage in 180nm CMOS process.

AB - This paper presents an 8-bit, 80MS/s Successive Approximation Register analog-to-digital converter (SAR ADC) with 2bit/cycle structure for sensor application. By using two capacitor-DAC arrays, S-DAC and R-DAC, the proposed SAR ADC can obtain 2-bit in one comparison cycle. With split-capacitor structure and monotonic switching strategy, two DACs reduce the number of capacitors and save the ADC power consumption. The proposed asynchronous control logic speeds up the ADC. The proposed ADC achieves 46.17dB SNDR at 80MS/s rate with 1.8V supply voltage in 180nm CMOS process.

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KW - split-capacitor

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M3 - Conference contribution

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BT - 2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

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Zhang L, Lou W, Gao Y. An 8-bit 80MS/s 2b/cycle SAR ADC for Sensor Application. In 2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. 8634360. (2018 12th International Symposium on Antennas, Propagation and EM Theory, ISAPE 2018 - Proceedings). doi: 10.1109/ISAPE.2018.8634360

An 8-bit 80MS/s 2b/cycle SAR ADC for Sensor Application

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