Abstract
A concurrent error detection design was proposed for discrete cosine transform, and based on it an improved design was presented. DCT is realized by butterfly architecture of B.G.Lee fast algorithm, and algorithm-based fault tolerance is used for CED. The proposed design allows 100% throughput and high fault coverage with a very low increment of hardware coverage. The fault coverage of this scheme was analyzed and the conclusion was given.
Original language | English |
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Pages (from-to) | 30-33 |
Number of pages | 4 |
Journal | Tien Tzu Hsueh Pao/Acta Electronica Sinica |
Volume | 27 |
Issue number | 8 |
Publication status | Published - Aug 1999 |
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Chen, H., Mao, Z., & Ye, Y. (1999). Algorithm-based concurrent error detection scheme for DCT networks. Tien Tzu Hsueh Pao/Acta Electronica Sinica, 27(8), 30-33.