A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance

Zhaozhi Yang; Zeyi Wang; Shuzhou Fang

doi:10.1109/ASPDAC.2001.913307

A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance

Zhaozhi Yang, Zeyi Wang, Shuzhou Fang

Tsinghua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors is replaced with a mesh charge distribution, and we use the multipole-accelerated algorithm to further depress the computational complexity. Numerical results show that its computational complexity is about O(n), where n is the number of the discrete variables. Within the comparable accuracy, it runs several times faster than Fastcap, which is presently a very advanced multipole-accelerated parasitic capacitance extractor.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2001
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2001
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	214-217
Number of pages	4
ISBN (Electronic)	0780366336
DOIs	https://doi.org/10.1109/ASPDAC.2001.913307
Publication status	Published - 2001
Externally published	Yes
Event	Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan Duration: 30 Jan 2001 → 2 Feb 2001

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2001-January

Conference

Conference	Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
Country/Territory	Japan
City	Yokohama
Period	30/01/01 → 2/02/01

Keywords

Acceleration
Computational complexity
Computer science
Conductors
Delay
Integral equations
Integrated circuit interconnections
Parasitic capacitance
Very large scale integration
Wires

Access to Document

10.1109/ASPDAC.2001.913307

Cite this

Yang, Z., Wang, Z., & Fang, S. (2001). A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001 (pp. 214-217). Article 913307 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2001.913307

Yang, Zhaozhi ; Wang, Zeyi ; Fang, Shuzhou. / A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., 2001. pp. 214-217 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{c6774d7e31bd4bf79ac583ecf035549c,

title = "A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance",

abstract = "A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors is replaced with a mesh charge distribution, and we use the multipole-accelerated algorithm to further depress the computational complexity. Numerical results show that its computational complexity is about O(n), where n is the number of the discrete variables. Within the comparable accuracy, it runs several times faster than Fastcap, which is presently a very advanced multipole-accelerated parasitic capacitance extractor.",

keywords = "Acceleration, Computational complexity, Computer science, Conductors, Delay, Integral equations, Integrated circuit interconnections, Parasitic capacitance, Very large scale integration, Wires",

author = "Zhaozhi Yang and Zeyi Wang and Shuzhou Fang",

note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 ; Conference date: 30-01-2001 Through 02-02-2001",

year = "2001",

doi = "10.1109/ASPDAC.2001.913307",

language = "English",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "214--217",

booktitle = "Proceedings of the ASP-DAC 2001",

address = "United States",

}

Yang, Z, Wang, Z & Fang, S 2001, A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. in Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001., 913307, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2001-January, Institute of Electrical and Electronics Engineers Inc., pp. 214-217, Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001, Yokohama, Japan, 30/01/01. https://doi.org/10.1109/ASPDAC.2001.913307

A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. / Yang, Zhaozhi; Wang, Zeyi; Fang, Shuzhou.
Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 214-217 913307 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance

AU - Yang, Zhaozhi

AU - Wang, Zeyi

AU - Fang, Shuzhou

PY - 2001

Y1 - 2001

N2 - A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors is replaced with a mesh charge distribution, and we use the multipole-accelerated algorithm to further depress the computational complexity. Numerical results show that its computational complexity is about O(n), where n is the number of the discrete variables. Within the comparable accuracy, it runs several times faster than Fastcap, which is presently a very advanced multipole-accelerated parasitic capacitance extractor.

AB - A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors is replaced with a mesh charge distribution, and we use the multipole-accelerated algorithm to further depress the computational complexity. Numerical results show that its computational complexity is about O(n), where n is the number of the discrete variables. Within the comparable accuracy, it runs several times faster than Fastcap, which is presently a very advanced multipole-accelerated parasitic capacitance extractor.

KW - Acceleration

KW - Computational complexity

KW - Computer science

KW - Conductors

KW - Delay

KW - Integral equations

KW - Integrated circuit interconnections

KW - Parasitic capacitance

KW - Very large scale integration

KW - Wires

UR - http://www.scopus.com/inward/record.url?scp=0011711525&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2001.913307

DO - 10.1109/ASPDAC.2001.913307

M3 - Conference contribution

AN - SCOPUS:0011711525

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 214

EP - 217

BT - Proceedings of the ASP-DAC 2001

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001

Y2 - 30 January 2001 through 2 February 2001

ER -

Yang Z, Wang Z, Fang S. A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 214-217. 913307. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2001.913307

A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this