@inproceedings{c6774d7e31bd4bf79ac583ecf035549c,
title = "A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance",
abstract = "A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors is replaced with a mesh charge distribution, and we use the multipole-accelerated algorithm to further depress the computational complexity. Numerical results show that its computational complexity is about O(n), where n is the number of the discrete variables. Within the comparable accuracy, it runs several times faster than Fastcap, which is presently a very advanced multipole-accelerated parasitic capacitance extractor.",
keywords = "Acceleration, Computational complexity, Computer science, Conductors, Delay, Integral equations, Integrated circuit interconnections, Parasitic capacitance, Very large scale integration, Wires",
author = "Zhaozhi Yang and Zeyi Wang and Shuzhou Fang",
note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 ; Conference date: 30-01-2001 Through 02-02-2001",
year = "2001",
doi = "10.1109/ASPDAC.2001.913307",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "214--217",
booktitle = "Proceedings of the ASP-DAC 2001",
address = "United States",
}