A single channel 2GS/s 6-bit ADC with cascade resistive averaging

Youtao Zhang*, Xiaopeng Li, Ao Liu, Ming Zhang, Feng Qian

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Citations (Scopus)

Abstract

A single channel 2GS/s 6-bit ADC with cascade resistive averaging is demonstrated in 0.18μm CMOS. The proposed power efficient crossing connection method of averaging resistors has less reference voltage consumed than convention with excellent offset averaging. The peak DNL and INL are measured as 0.26 LSB and 0.21 LSB, respectively. The SNDR and SFDR have achieved 34.2 and 37.5dB, respectively, with 1.22 MHz input signal and 2GS/s. The SNDR and SFDR maintain above 30 and 35dB, respectively, up to1000MHz input signal and 900MS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8V supply while operating at 2GS/s.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages195-198
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
Duration: 20 Oct 200923 Oct 2009

Publication series

NameASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Conference

Conference2009 8th IEEE International Conference on ASIC, ASICON 2009
Country/TerritoryChina
CityChangsha
Period20/10/0923/10/09

Keywords

  • Analog-to-digital conversion
  • Flash
  • Interpolation
  • Offset averaging

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